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    MEMORY CHIP CONNECTING A SYSTEM ON A CHIP AND AN ACCELERATOR CHIP
    3.
    发明申请
    MEMORY CHIP CONNECTING A SYSTEM ON A CHIP AND AN ACCELERATOR CHIP 有权

    公开(公告)号：US20220300437A1

    公开(公告)日：2022-09-22

    申请号：US17837565

    申请日：2022-06-10

    Applicant: Micron Technology, Inc.

    Inventor： Sean S. Eilert ,  Kenneth Marion Curewitz ,  Justin M. Eno

    IPC: G06F13/16 ,  G06F9/30

    Abstract: A memory chip (e.g., DRAM) connecting a SoC and an accelerator chip (e.g., an AI accelerator chip). A system including the memory chip and the accelerator chip. The system can include the SoC. The memory chip can include first memory cells to store and provide computation input data (e.g., AI computation input data) received from the SoC to be used by the accelerator chip as computation input (e.g., AI computation input). The memory chip can include second memory cells to store and provide first computation output data (e.g., AI computation output data) received from the accelerator chip to be retrieved by the SoC or reused by the accelerator chip as computation input. The memory chip can also include third memory cells to store second computation output data (e.g., non-AI computation output data) related to non-AI tasks received from the SoC to be retrieved by the SoC for non-AI tasks.

    Time to live for memory access by processors
    4.
    发明授权
    Time to live for memory access by processors 有权

    公开(公告)号：US11243804B2

    公开(公告)日：2022-02-08

    申请号：US16688245

    申请日：2019-11-19

    Applicant: Micron Technology, Inc.

    Inventor： Justin M. Eno

    IPC: G06F9/46 ,  G06F9/48

    Abstract: Systems, apparatuses, and methods to implement time to live for memory access by processors. For example, a processor has a register configured to store a parameter specifying a time duration indicative of the desired time to live. A memory system has multiple components with different latencies for memory access. When the memory controller of the processor sends a command to the memory system to load an item from a memory address, the memory system can fail to provide, to the processor within the time duration, the item from the memory address currently being hosted in a first component. In response, the memory controller can send a signal to abort the command; and the memory system can select a second component having a memory access latency shorter than the first component, and change the hosting of the memory address from in the first component to in the second component.

    Time to live for load commands
    5.
    发明授权
    Time to live for load commands 有权

    公开(公告)号：US11199995B2

    公开(公告)日：2021-12-14

    申请号：US16688250

    申请日：2019-11-19

    Applicant: Micron Technology, Inc.

    Inventor： Shivasankar Gunasekaran ,  Samuel E. Bradshaw ,  Justin M. Eno ,  Ameen D. Akel

    IPC: G06F3/06 ,  G06F12/0873 ,  G06F11/07

    Abstract: A memory sub-system configured to be responsive to a time to live requirement for load commands from a processor. For example, a load command issued by the processor (e.g., SoC) can include, or be associated with, an optional time to live parameter. The parameter requires that the data at the memory address be available within the time specified by the time to live parameter. When the requested data is currently in the lower speed memory (e.g., NAND flash) and not available in the higher speed memory (e.g., DRAM, NVRAM), the memory subsystem can determine that the data cannot be made available with the specified time and optionally skip the operations and return an error response immediately.

    PAGE TABLE HOOKS TO MEMORY TYPES
    6.
    发明申请
    PAGE TABLE HOOKS TO MEMORY TYPES 有权

    公开(公告)号：US20210081324A1

    公开(公告)日：2021-03-18

    申请号：US16573527

    申请日：2019-09-17

    Applicant: Micron Technology, Inc.

    Inventor： Samuel E. Bradshaw ,  Justin M. Eno ,  Sean S. Eilert ,  Shivasankar Gunasekaran ,  Hongyu Wang ,  Shivam Swami

    IPC: G06F12/1009 ,  G06F12/1027

    Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.

    Performing data restore operations in memory
    7.
    发明授权
    Performing data restore operations in memory 有权

    公开(公告)号：US10445195B2

    公开(公告)日：2019-10-15

    申请号：US15670544

    申请日：2017-08-07

    Applicant: Micron Technology, Inc.

    Inventor： Samuel E. Bradshaw ,  Justin M. Eno

    IPC: G06F11/07 ,  G06F11/14 ,  G06F3/06 ,  G06F1/3225

    Abstract: The present disclosure includes apparatuses and methods for performing data restore operations in memory. An embodiment includes a memory, and a controller configured to perform a data restore operation on data stored in the memory using a first table and a second table stored in the controller, wherein the first table includes a current mapping of the data stored in the memory that is based on a previous assessment of previous error rates associated with the data stored in the memory, and the second table includes a new mapping of the data stored in the memory that is based on a current assessment of current error rates associated with the data stored in the memory.

    PERFORMING DATA RESTORE OPERATIONS IN MEMORY
    8.
    发明申请
    PERFORMING DATA RESTORE OPERATIONS IN MEMORY 审中-公开

    公开(公告)号：US20190278670A1

    公开(公告)日：2019-09-12

    申请号：US16423574

    申请日：2019-05-28

    Applicant: Micron Technology, Inc.

    Inventor： Samuel E. Bradshaw ,  Justin M. Eno

    IPC: G06F11/14 ,  G06F3/06 ,  G06F1/3225

    Abstract: The present disclosure includes apparatuses and methods for performing data restore operations in memory. An embodiment includes a memory, and a controller configured to perform a data restore operation on data stored in the memory using a first table and a second table stored in the controller, wherein the first table includes a current mapping of the data stored in the memory that is based on a previous assessment of previous error rates associated with the data stored in the memory, and the second table includes a new mapping of the data stored in the memory that is based on a current assessment of current error rates associated with the data stored in the memory.

    MEMORY CHIP HAVING AN INTEGRATED DATA MOVER
    9.
    发明申请
    MEMORY CHIP HAVING AN INTEGRATED DATA MOVER 有权

    公开(公告)号：US20240427708A1

    公开(公告)日：2024-12-26

    申请号：US18828657

    申请日：2024-09-09

    Applicant: Micron Technology, Inc.

    Inventor： Samuel E. Bradshaw ,  Shivam Swami ,  Sean Stephen Eilert ,  Justin M. Eno ,  Ameen D. Akel

    IPC: G06F13/10 ,  G06F3/06 ,  G06F12/0802 ,  G06F13/12

    Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.

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