公开(公告)号：US20240330009A1

公开(公告)日：2024-10-03

申请号：US18738523

申请日：2024-06-10

Applicant: Micron Technology, Inc.

Inventor： Sourin SARKAR ,  Vamshikrishna KOMURAVELLI ,  Kanika MITTAL

IPC: G06F9/4401

CPC classification number: G06F9/4411 ,  G06F9/4418

Abstract: Implementations described herein relate to boot processes for memory devices. In some implementations, a controller of a storage system receives a command for enabling a fast bootup process for the storage system. The fast bootup process may exclude a measurement of information retrieved from a memory device of the storage system during the fast bootup process. The controller may enable the fast bootup process based on the command. The controller may disable a normal bootup process for the storage system based on the fast bootup process being enabled. The normal bootup process may include a measurement of information retrieved from the memory device during the normal bootup process.

公开(公告)号：US20250103707A1

公开(公告)日：2025-03-27

申请号：US18781301

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Sourin SARKAR ,  Kiran K. GUNNAM ,  Chittoor Ranganathan PARTHASARATHY

IPC: G06F21/55 ,  G06F21/60 ,  G06F21/78

Abstract: In some implementations, a memory device may include one or more components. The one or more components may be configured to identify an operation to access content stored in a memory of the memory device, wherein the operation is associated with a user profile. The one or more components may be configured to flag a user, associated with the user profile, as being potentially malicious based on the operation conflicting with a past content access pattern associated with the user profile. The one or more components may be configured to lock the memory based on the user being flagged.

公开(公告)号：US20230393763A1

公开(公告)日：2023-12-07

申请号：US17834547

申请日：2022-06-07

Applicant: Micron Technology, Inc.

Inventor： Sourin SARKAR

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0679 ,  G06F3/0655

Abstract: Implementations described herein relate to protection against invalid memory commands. In some implementations, a memory device may include one or more components that may receive, from a host device, a pilot command that includes an indication of a sequence of upcoming memory commands to be transmitted from the host device to the memory device, receive a memory command from the host device after receiving the pilot command, determine that the memory command is invalid based on the indication of the sequence of upcoming memory commands, and transmit, to the host device and based on determining that the memory command is invalid, a message indicating that the memory command is invalid. Numerous other implementations are described.

公开(公告)号：US20230359466A1

公开(公告)日：2023-11-09

申请号：US17661983

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Sourin SARKAR ,  Vamshikrishna KOMURAVELLI ,  Kanika MITTAL

IPC: G06F9/4401

CPC classification number: G06F9/4411 ,  G06F9/4418

Abstract: Implementations described herein relate to boot processes for memory devices. In some implementations, a controller of a storage system receives a command for enabling a fast bootup process for the storage system. The fast bootup process may exclude a measurement of information retrieved from a memory device of the storage system during the fast bootup process. The controller may enable the fast bootup process based on the command. The controller may disable a normal bootup process for the storage system based on the fast bootup process being enabled. The normal bootup process may include a measurement of information retrieved from the memory device during the normal bootup process.

公开(公告)号：US20230344624A1

公开(公告)日：2023-10-26

申请号：US17725178

申请日：2022-04-20

Applicant: Micron Technology, Inc.

Inventor： Sourin SARKAR ,  Vamshikrishna KOMURAVELLI

IPC: H04L9/08 ,  H04L9/32

CPC classification number: H04L9/0866 ,  H04L9/3278

Abstract: In some implementations, a memory device may generate a physical unclonable function (PUF) value. The memory device may access a PUF protection key stored in a non-host-addressable memory region. The memory device may encrypt the PUF value, using the PUF protection key, to generate an encrypted PUF value. The memory device may store the encrypted PUF value in scattered memory locations in the non-host-addressable memory region.

公开(公告)号：US20250106014A1

公开(公告)日：2025-03-27

申请号：US18973806

申请日：2024-12-09

Applicant: Micron Technology, Inc.

Inventor： Sourin SARKAR ,  Vamshikrishna KOMURAVELLI

IPC: H04L9/08 ,  H04L9/32

Abstract: In some implementations, a memory device may generate a physical unclonable function (PUF) value. The memory device may access a PUF protection key stored in a non-host-addressable memory region. The memory device may encrypt the PUF value, using the PUF protection key, to generate an encrypted PUF value. The memory device may store the encrypted PUF value in scattered memory locations in the non-host-addressable memory region.

公开(公告)号：US20250068739A1

公开(公告)日：2025-02-27

申请号：US18941717

申请日：2024-11-08

Applicant: Micron Technology, Inc.

Inventor： Sourin SARKAR

IPC: G06F21/57 ,  G06F21/60 ,  G06F21/73 ,  H04L9/00

Abstract: Implementations described herein relate to establishing a chain of ownership of a device. In some implementations, the device may determine first ownership metadata based on first ownership data associated with the device. The device may split the first ownership metadata into a first portion of first ownership metadata and a second portion of first ownership metadata. The device may store, in the memory of the device, the first portion of first ownership metadata. The device may transmit, to a server, the second portion of first ownership metadata for storage in a blockchain ledger of a blockchain node. A chain of ownership associated with the device may be established based on a combination of the first portion of first ownership metadata stored in the memory of the device and the second portion of first ownership metadata stored in the blockchain ledger.

公开(公告)号：US20230394152A1

公开(公告)日：2023-12-07

申请号：US17858560

申请日：2022-07-06

Applicant: Micron Technology, Inc.

Inventor： Sourin SARKAR

IPC: G06F21/57 ,  G06F21/73 ,  G06F21/60 ,  H04L9/00

CPC classification number: G06F21/57 ,  G06F21/73 ,  G06F21/602 ,  H04L9/50

Abstract: Implementations described herein relate to establishing a chain of ownership of a device. In some implementations, the device may determine first ownership metadata based on first ownership data associated with the device. The device may split the first ownership metadata into a first portion of first ownership metadata and a second portion of first ownership metadata. The device may store, in the memory of the device, the first portion of first ownership metadata. The device may transmit, to a server, the second portion of first ownership metadata for storage in a blockchain ledger of a blockchain node. A chain of ownership associated with the device may be established based on a combination of the first portion of first ownership metadata stored in the memory of the device and the second portion of first ownership metadata stored in the blockchain ledger.

公开(公告)号：US20230391345A1

公开(公告)日：2023-12-07

申请号：US17858568

申请日：2022-07-06

Applicant: Micron Technology, Inc.

Inventor： Sourin SARKAR

IPC: B60W40/08 ,  G06F8/65 ,  H04W4/40

CPC classification number: B60W40/08 ,  B60W2040/0809 ,  H04W4/40 ,  G06F8/65

Abstract: In some implementations, a host processor associated with a vehicle may select, from a plurality of devices that are configured to communicate with the host processor for performing security functions, a first device to serve as a primary device and a second device to serve as a secondary device. The first device may include a first memory with an embedded hardware security module and may be associated with a first set of nodes of the vehicle. The second device may include a second memory with an embedded hardware security module and may be associated with a second set of nodes of the vehicle. The host processor may determine, based on a signal, a failure associated with the first device or the second device. The host processor may initiate a remediation process based on the failure associated with the first device or the second device. Numerous other implementations are described.

公开(公告)号：US20230300139A1

公开(公告)日：2023-09-21

申请号：US17697620

申请日：2022-03-17

Applicant: Micron Technology, Inc.

Inventor： Sourin SARKAR ,  Kanika MITTAL ,  Gowrishankar GAJENDIRAN

IPC: H04L9/40 ,  H04L9/00 ,  H04L67/12

CPC classification number: H04L63/102 ,  H04L9/006 ,  H04L63/08 ,  H04L67/12 ,  H04L2209/84

Abstract: In some implementations, a device of an Internet of Things (IoT) network may receive, from a host associated with the IoT network, information associated with the IoT network. The device may store, via a memory controller of the device, the information in a memory with an embedded hardware security module of the device, wherein the device serves as a root of trust for the host using the information stored in the memory. The device may receive, from the host, a request to perform a security function. The device may perform, based on the request, the security function using the information stored in the memory. The device may generate an alert based on an outcome of the security function. Numerous other implementations are described.