公开(公告)号：US20030185036A1

公开(公告)日：2003-10-02

申请号：US10109088

申请日：2002-03-28

Applicant: Micron Technology, Inc.

Inventor： Terry L. Gilton ,  John T. Moore

IPC: G11C017/00

CPC classification number: G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/009

Abstract: A method for reading and verifying the state of a memory cell during a write operation before writing allows a decision to be made whether to write to the cell or not based on the current state of the cell.

Abstract translation: 在写入之前的写入操作期间读取和验证存储器单元的状态的方法允许基于单元的当前状态来决定是否写入单元。

公开(公告)号：US20020175608A1

公开(公告)日：2002-11-28

申请号：US10193016

申请日：2002-07-09

Applicant: Micron Technology, Inc.

Inventor： Terry L. Gilton ,  Paul A. Morgan

IPC: H01J001/02

CPC classification number: H01J1/3042 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2329/00

Abstract: Improved methods and structures are provided for an array of vertical geometries which may be used as emitter tips, as a self aligned gate structure surrounding field emitter tips, or as part of a flat panel display. The present invention offers controlled size in emitter tip formation under a more streamlined process. The present invention further provides a more efficient method to control the gate to emitter tip proximity in field emission devices. The novel method of the present invention includes implanting a dopant in a patterned manner into the silicon substrate and anodizing the silicon substrate in a controlled manner causing a more heavily doped region in the silicon substrate to form a porous silicon region.

Abstract translation: 提供了用于垂直几何阵列的改进的方法和结构，其可以用作发射器尖端，作为围绕场发射器尖端的自对准栅极结构，或者作为平板显示器的一部分。 本发明在更简化的过程中提供了在发射极尖端形成中的受控尺寸。 本发明还提供了一种更有效的方法来控制场致发射器件中的栅极与发射极尖端的接近。 本发明的新颖方法包括以图案化的方式将掺杂剂注入到硅衬底中并以受控的方式对硅衬底进行阳极氧化，从而在硅衬底中形成更重掺杂的区域以形成多孔硅区域。

公开(公告)号：US20040038432A1

公开(公告)日：2004-02-26

申请号：US10618824

申请日：2003-07-14

Applicant: Micron Technology, Inc.

Inventor： Terry L. Gilton

IPC: H01L021/00

CPC classification number: H01L45/143 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/1641 ,  H01L45/1658 ,  H01L45/1675 ,  H01L45/1683

Abstract: In programmable conductor memory cells, metal ions precipitate out of a glass electrolyte element in response to an applied electric field in one direction only, causing a conductive pathway to grow from cathode to anode. The amount of conductive pathway growth, and therefore the programming, depends, in part, on the availability of metal ions. It is important that the metal ions come only from the solid solution of the memory cell body. If additional metal ions are supplied from other sources, such as the sidewall edge at the anode interface, the amount of metal ions may not be directly related to the strength of the electric field, and the programming will not respond consistently from cell to cell. The embodiments described herein provide new and novel structures that block interface diffusion paths for metal ions, leaving diffusion from the bulk glass electrolyte as the only supply of metal ions for conductive pathway formation.

Abstract translation: 在可编程导体存储单元中，金属离子响应于仅在一个方向施加的电场而从玻璃电解质元件中沉淀出来，导致导电通路从阴极生长到阳极。 导电路径生长的量，因此编程的数量部分地取决于金属离子的可用性。 重要的是金属离子仅来自存储单元体的固溶体。 如果从其他来源（如阳极界面处的侧壁边缘）提供额外的金属离子，则金属离子的量可能与电场的强度无关，编程将不会从单元到单元一致地反应。 本文所述的实施方案提供了新的和新颖的结构，其阻止金属离子的界面扩散路径，留下从本体玻璃电解质的扩散作为导电通路形成的唯一金属离子供应。

公开(公告)号：US20040043585A1

公开(公告)日：2004-03-04

申请号：US10231779

申请日：2002-08-29

Applicant: Micron Technology, Inc.,

Inventor： John T. Moore ,  Terry L. Gilton ,  Kristy A. Campbell

IPC: H01L021/336

CPC classification number: H01L45/1675 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/143 ,  H01L45/1641

Abstract: The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a metal-rich metal chalcogenide, such as, for example, silver-rich silver selenide. Advantageously, the processes can form the metal-rich metal chalcogenide without the use of photodoping techniques and without direct deposition of the metal. For example, the process can remove selenium from silver selenide. One embodiment of the process implants oxygen to silver selenide to form selenium oxide. The selenium oxide is then removed by annealing, which results in silver-rich silver selenide. Advantageously, the processes can dope silver into a variety of materials, including non-transparent materials, with relatively high uniformity and with relatively precise control.

Abstract translation: 本发明涉及电阻可变材料单元或可编程金属化单元的制造。 本文所述的方法可形成金属富金属硫族化物，例如富银硒化银。 有利的是，该方法可以形成富含金属的金属硫属元素化物，而不需要使用光致激发技术，而不会直接沉积金属。 例如，该过程可以从硒化银中除去硒。 该方法的一个实施方案是将氧沉积到硒化银以形成氧化硒。 然后通过退火除去氧化硒，这导致富银银硒化银。 有利的是，该方法可以将银掺杂到各种材料中，包括非透明材料，具有相对高的均匀性和相对精确的控制。

公开(公告)号：US20010038111A1

公开(公告)日：2001-11-08

申请号：US09864552

申请日：2001-05-23

Applicant: Micron Technology, Inc.

Inventor： Scott J. DeBoer ,  Terry L. Gilton ,  Ceredig Roberts

IPC: H01L021/8234

CPC classification number: H01L21/76897 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L28/40 ,  H01L28/90

Abstract: An etching method includes providing a first insulating material layer on a substrate assembly surface and a second insulating material layer on the first insulating material layer. The first insulating material layer has an etch rate that is greater than the etch rate of the second insulating material layer when exposed to an etch composition. Portions of the first insulating material layer and the second insulating material layer are removed using at least the etch composition. Various types of structures (e.g., contacts, capacitors) are formed with use of the method.

Abstract translation: 蚀刻方法包括在第一绝缘材料层上在衬底组装表面上提供第一绝缘材料层和第二绝缘材料层。 当暴露于蚀刻组合物时，第一绝缘材料层具有大于第二绝缘材料层的蚀刻速率的蚀刻速率。 至少使用蚀刻组合物去除第一绝缘材料层和第二绝缘材料层的部分。 使用该方法形成各种类型的结构（例如，触点，电容器）。