公开(公告)号：US20020151191A1

公开(公告)日：2002-10-17

申请号：US10160698

申请日：2002-05-30

Applicant: Micron Technology, Inc.

Inventor： Scott Jeffrey DeBoer ,  John T. Moore

IPC: H01L021/31

CPC classification number: H01L21/0332 ,  H01L21/28123 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3185 ,  H01L21/32139 ,  Y10S438/942 ,  Y10S438/944

Abstract: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material, and patterned. A pattern is then transferred from the patterned imagable material to the first and second materials. The invention also includes a structure comprising a first layer of silicon nitride over a substrate, and a second layer on the first layer. The second layer comprises silicon and is free of nitrogen. The structure further comprises a third layer consisting essentially of imagable material on the second layer.

Abstract translation: 本发明包括半导体处理方法。 形成包含硅和氮的第一材料。 在第一材料上形成第二材料，并且第二材料包含硅和少于第一材料的原子百分比的氮。 在第二材料上形成可成像的材料并图案化。 然后将图案从图案化的可成像材料转移到第一和第二材料。 本发明还包括在衬底上包括第一氮化硅层的结构，以及在第一层上的第二层。 第二层包括硅并且不含氮。 该结构还包括基本上由第二层上的可成像材料组成的第三层。

公开(公告)号：US20040222441A1

公开(公告)日：2004-11-11

申请号：US10859016

申请日：2004-06-01

Applicant: Micron Technology, Inc.

Inventor： John T. Moore

IPC: H01L027/10

CPC classification number: H01L27/101 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855

Abstract: An integrated circuit chip comprises a periphery portion and a memory portion. The memory portion includes a data storage layer and a logic layer formed underneath the data storage layer and is separated therefrom by an intermediate layer. A first conductive layer is formed within the intermediate layer to communicatively couple the periphery and memory portions of the integrated circuit chip, and a second conductive layer is formed within the intermediate layer to communicatively couple the periphery and memory portions of the integrated circuit chip. The first and second conductive layers provide addressing and data retrieval between the memory portion and the periphery portion.

公开(公告)号：US20030185036A1

公开(公告)日：2003-10-02

申请号：US10109088

申请日：2002-03-28

Applicant: Micron Technology, Inc.

Inventor： Terry L. Gilton ,  John T. Moore

IPC: G11C017/00

CPC classification number: G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/009

Abstract: A method for reading and verifying the state of a memory cell during a write operation before writing allows a decision to be made whether to write to the cell or not based on the current state of the cell.

Abstract translation: 在写入之前的写入操作期间读取和验证存储器单元的状态的方法允许基于单元的当前状态来决定是否写入单元。

公开(公告)号：US20030096497A1

公开(公告)日：2003-05-22

申请号：US09988984

申请日：2001-11-19

Applicant: Micron Technology, Inc.

Inventor： John T. Moore ,  Joseph F. Brooks

IPC: H01L021/44

CPC classification number: H01L24/05 ,  G11C13/0011 ,  G11C2213/79 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76867 ,  H01L24/03 ,  H01L45/085 ,  H01L45/124 ,  H01L45/143 ,  H01L45/1658 ,  H01L45/1683 ,  H01L2224/05006 ,  H01L2224/05546 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01028 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3011 ,  Y10S438/957 ,  H01L2924/00

Abstract: An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.

Abstract translation: 电极结构包括第一层导电材料和形成在第一层表面上的电介质层。 在电介质层中形成开口以露出第一层表面的一部分。 在电介质层上和第一层的表面的暴露部分上形成粘合层，并且在导电结合层上形成第二导电材料层。 结合层可以是氧化物，第二层是可扩散到氧化物中的导电材料。 可以将电极结构退火以使来自第二层的导电材料被化学吸附到结合层中，以改善第一和第二层之间的粘附。 可以通过在电极结构中形成掺杂的玻璃层来形成可编程单元。

公开(公告)号：US20040164336A1

公开(公告)日：2004-08-26

申请号：US10789981

申请日：2004-03-02

Applicant: Micron Technology, Inc.

Inventor： Ronald A. Weimer ,  John T. Moore

IPC: H01L027/108

CPC classification number: H01L21/0276 ,  H01L21/02126 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/3145 ,  H01L21/3146 ,  H01L21/3148 ,  H01L21/31604 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/91 ,  Y10S257/90 ,  Y10S438/97

Abstract: The invention pertains to films comprising silicon, oxygen and carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies.

Abstract translation: 本发明涉及包含硅，氧和碳的薄膜以及集成电路技术中的薄膜的使用，例如电容器结构，DRAM结构，半导体材料组件，蚀刻工艺以及用于形成电容器，DRAM和半导体材料组件的方法。

公开(公告)号：US20040043585A1

公开(公告)日：2004-03-04

申请号：US10231779

申请日：2002-08-29

Applicant: Micron Technology, Inc.,

Inventor： John T. Moore ,  Terry L. Gilton ,  Kristy A. Campbell

IPC: H01L021/336

CPC classification number: H01L45/1675 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/143 ,  H01L45/1641

Abstract: The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a metal-rich metal chalcogenide, such as, for example, silver-rich silver selenide. Advantageously, the processes can form the metal-rich metal chalcogenide without the use of photodoping techniques and without direct deposition of the metal. For example, the process can remove selenium from silver selenide. One embodiment of the process implants oxygen to silver selenide to form selenium oxide. The selenium oxide is then removed by annealing, which results in silver-rich silver selenide. Advantageously, the processes can dope silver into a variety of materials, including non-transparent materials, with relatively high uniformity and with relatively precise control.

Abstract translation: 本发明涉及电阻可变材料单元或可编程金属化单元的制造。 本文所述的方法可形成金属富金属硫族化物，例如富银硒化银。 有利的是，该方法可以形成富含金属的金属硫属元素化物，而不需要使用光致激发技术，而不会直接沉积金属。 例如，该过程可以从硒化银中除去硒。 该方法的一个实施方案是将氧沉积到硒化银以形成氧化硒。 然后通过退火除去氧化硒，这导致富银银硒化银。 有利的是，该方法可以将银掺杂到各种材料中，包括非透明材料，具有相对高的均匀性和相对精确的控制。