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33 条记录 (耗时 0.022 秒)

    MRAM device integrated with other types of circuitry
    1.
    发明授权
    MRAM device integrated with other types of circuitry 有权
    与其他类型电路集成的MRAM器件

    公开(公告)号：US07031183B2

    公开(公告)日：2006-04-18

    申请号：US10730239

    申请日：2003-12-08

    申请人： Gloria J. Kerszykowski ,  Li Hsin Chang ,  Mark A. Durlam ,  Mitchell T. Lien ,  Thomas V. Meixner ,  Loren J. Wise

    发明人： Gloria J. Kerszykowski ,  Li Hsin Chang ,  Mark A. Durlam ,  Mitchell T. Lien ,  Thomas V. Meixner ,  Loren J. Wise

    IPC分类号： G11C7/00

    CPC分类号： G11C11/15

    摘要： A magnetoresistive random access memory (MRAM) is embedded with another circuit type. Logic, such as a processing unit, is particularly well-suited circuit type for embedding with MRAM. The embedding is made more efficient by using a metal layer that is used as part of the interconnect for the other circuit also as part of the MRAM cell. The MRAM cells are all written by program lines, which are the two lines that cross to define a cell to be written. Thus, the design is simplified because there is commonality of usage of the metal line that is used for one of the program lines for the MRAM and for one of the interconnect lines for the logic.

    摘要翻译： 磁阻随机存取存储器（MRAM）嵌入另一种电路类型。 诸如处理单元之类的逻辑特别适用于用MRAM嵌入的电路类型。 通过使用金属层作为MRAM单元的一部分，作为用于另一电路的互连部分的金属层，使嵌入更加有效。 MRAM单元全部由程序行写入，它们是用于定义要写入的单元格的两条线。 因此，简化了设计，因为对于用于MRAM的程序行之一和用于逻辑的互连线之一的金属线的使用是共同的。

    Magnetoresistive random access memory device structures and methods for fabricating the same
    2.
    发明授权
    Magnetoresistive random access memory device structures and methods for fabricating the same 有权
    磁阻随机存取存储器件结构及其制造方法

    公开(公告)号：US07144744B2

    公开(公告)日：2006-12-05

    申请号：US10977003

    申请日：2004-10-27

    申请人： Mitchell T. Lien ,  Mark A. Durlam ,  Thomas V. Meixner ,  Loren J. Wise

    发明人： Mitchell T. Lien ,  Mark A. Durlam ,  Thomas V. Meixner ,  Loren J. Wise

    IPC分类号： H01L21/00

    CPC分类号： H01L43/12 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76843

    摘要： Magnetoelectronic memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line disposed at least partially within a dielectric layer. The dielectric material layer overlies an interconnect stack. A void space is etched in the dielectric layer to expose the interconnect stack. A conductive-barrier layer having a first portion and a second portion is deposited. The first portion overlies the digit line and the second portion is disposed within the void space and in electrical communication with the interconnect stack. A memory element layer is formed overlying the first portion and an electrode layer is deposited overlying the memory element layer. The electrode layer and the memory element layer are then patterned and etched.

    摘要翻译： 提供了使用阻挡层作为材料去除停止层来制造这种结构的磁电存储元件结构和方法。 所述方法包括形成至少部分地设置在电介质层内的数字线。 电介质材料层覆盖互连叠层。 在电介质层中蚀刻空隙以暴露互连叠层。 沉积具有第一部分和第二部分的导电阻挡层。 第一部分覆盖数字线，第二部分设置在空隙空间内并与互连叠层电连通。 形成覆盖在第一部分上的存储元件层，并且沉积覆盖存储元件层的电极层。 然后对电极层和存储元件层进行图案化和蚀刻。

    Methods and apparatus for a memory device with self-healing reference bits
    4.
    发明授权
    Methods and apparatus for a memory device with self-healing reference bits 有权
    具有自修复参考位的存储器件的方法和装置

    公开(公告)号：US07747926B2

    公开(公告)日：2010-06-29

    申请号：US11416850

    申请日：2006-05-02

    申请人： Loren J. Wise ,  Thomas W. Andre ,  Mark A. Durlam ,  Eric J. Salter

    发明人： Loren J. Wise ,  Thomas W. Andre ,  Mark A. Durlam ,  Eric J. Salter

    IPC分类号： G11C29/00

    CPC分类号： G11C29/52 ,  G06F11/1008 ,  G11C11/16

    摘要： A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits (104) is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit (104) is toggled back to its original state.

    摘要翻译： 诸如MRAM设备的存储器件包括与一组阵列位（102）相关联的自修复参考位（104）。 存储器执行错误检测步骤（例如，使用纠错编码（ECC）算法）来检测数据位内的一组错误的存在，其中一个参考位（104）被切换到不同的状态，如果 错误计数大于预定阈值，如果随后读取的错误集合保持不变，则将参考位（104）切换回其初始状态。

    Magnetic tunnel junction temperature sensors and methods
    7.
    发明授权
    Magnetic tunnel junction temperature sensors and methods 失效
    磁隧道结温度传感器及方法

    公开(公告)号：US07510883B2

    公开(公告)日：2009-03-31

    申请号：US11239884

    申请日：2005-09-30

    申请人： Young Sir Chung ,  Robert W. Baird ,  Mark A. Durlam

    发明人： Young Sir Chung ,  Robert W. Baird ,  Mark A. Durlam

    IPC分类号： H01L21/00 ,  H01L27/14

    CPC分类号： H01L27/228 ,  G01K7/36 ,  Y10T428/1114

    摘要： Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit are provided. According to one exemplary method, a Magnetic Tunnel Junction (“MTJ”) temperature sensor is provided over the heat source. The MTJ temperature sensor comprises an MTJ core configured to output a current during operation thereof. The value of the current varies based on a resistance value of the particular MTJ core. The resistance value of the MTJ core varies as a function of the temperature of the heat source. A value of the current of the MTJ core can then be associated with a corresponding temperature of the heat source.

    摘要翻译： 提供了感测设置在集成电路的基板中的热源的温度的技术。 根据一个示例性方法，在热源上提供磁隧道结（“MTJ”）温度传感器。 MTJ温度传感器包括被配置为在其操作期间输出电流的MTJ内核。 电流值根据特定MTJ磁芯的电阻值而变化。 MTJ芯的电阻值随着热源的温度而变化。 然后，MTJ芯的电流的值可以与热源的相应温度相关联。

    3-D inductor and transformer devices in MRAM embedded integrated circuits
    8.
    发明授权
    3-D inductor and transformer devices in MRAM embedded integrated circuits 失效
    3-D电感和变压器装置在MRAM嵌入式集成电路中

    公开(公告)号：US07262069B2

    公开(公告)日：2007-08-28

    申请号：US11147599

    申请日：2005-06-07

    申请人： Young Sir Chung ,  Robert W. Baird ,  Mark A. Durlam ,  Bradley N. Engel

    发明人： Young Sir Chung ,  Robert W. Baird ,  Mark A. Durlam ,  Bradley N. Engel

    IPC分类号： H01L21/00

    CPC分类号： H01L27/222 ,  G11C11/16 ,  H01F17/0006 ,  H01F19/04 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and at least one inductance element formed on the same substrate using the same fabrication process technology. The inductance element, which may be an inductor or a transformer, is formed at the same metal layer (or layers) as the program lines of the MRAM architecture. Any available metal layer in addition to the program line layers can be added to the inductance element to enhance its efficiency. The concurrent fabrication of the MRAM architecture and the inductance element facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.

    摘要翻译： 集成电路器件包括磁性随机存取存储器（“MRAM”）结构以及使用相同的制造工艺技术在同一衬底上形成的至少一个电感元件。 可以是电感器或变压器的电感元件形成在与MRAM架构的程序线相同的金属层（或多层）上。 除了编程线层之外，可以将任何可用的金属层添加到电感元件以增强其效率。 MRAM架构和电感元件的并发制造有助于在衬底的有源电路块上可用的物理空间的有效和成本有效的使用，从而导致三维集成。

    Magnetoresistive random access memory devices and methods for fabricating the same
    9.
    发明授权
    Magnetoresistive random access memory devices and methods for fabricating the same 有权
    磁阻随机存取存储器件及其制造方法

    公开(公告)号：US07169622B2

    公开(公告)日：2007-01-30

    申请号：US10912979

    申请日：2004-08-05

    申请人： Gregory W. Grynkewich ,  Brian R. Butcher ,  Mark A. Durlam ,  Clarence J. Tracy

    发明人： Gregory W. Grynkewich ,  Brian R. Butcher ,  Mark A. Durlam ,  Clarence J. Tracy

    IPC分类号： H01L21/00

    CPC分类号： G11C11/16 ,  B82Y10/00 ,  H01L27/228

    摘要： Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.

    摘要翻译： 制造磁阻随机存取存储器单元和用于磁阻随机存取存储单元的结构开始于提供其中形成有晶体管的衬底。 形成电耦合到晶体管的接触元件，并且电介质材料沉积在由接触元件部分界定的区域内。 在电介质材料内形成数字线，数字线覆盖接触元件的一部分。 导电层形成在数字线上方并与接触元件电连通。

    MRAM and methods for reading the MRAM
    10.
    发明授权
    MRAM and methods for reading the MRAM 有权
    MRAM和读取MRAM的方法

    公开(公告)号：US06909631B2

    公开(公告)日：2005-06-21

    申请号：US10679134

    申请日：2003-10-02

    申请人： Mark A. Durlam ,  Thomas W. Andre ,  Mark F. DeHerrera ,  Bradley N. Engel ,  Bradley J. Garni ,  Joseph J. Nahas ,  Nicholas D. Rizzo ,  Saied Tehrani

    发明人： Mark A. Durlam ,  Thomas W. Andre ,  Mark F. DeHerrera ,  Bradley N. Engel ,  Bradley J. Garni ,  Joseph J. Nahas ,  Nicholas D. Rizzo ,  Saied Tehrani

    IPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/14

    CPC分类号： G11C11/16 ,  G11C11/15

    摘要： An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.

    摘要翻译： 提供了一种MRAM，其通过利用每个存储单元中的隔离或选择装置来最小化MRAM密度的限制。 另外，提供了用于读取MRAM的联动存储单元中的MTJ的方法。 该方法包括确定至少部分地与MRAM的联动存储器单元的电阻相关联的电气值。 切换联合存储器单元中的MTJ，并且在切换MTJ之后确定至少部分地与组合存储器单元的电阻相关联的第二电值。 一旦确定了切换之前和切换之后的电气值，则分析两个电气值之间的差异，以确定MTJ的值。