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    Methods and apparatus for a memory device with self-healing reference bits
    1.
    发明授权
    Methods and apparatus for a memory device with self-healing reference bits 有权
    具有自修复参考位的存储器件的方法和装置

    公开(公告)号：US07747926B2

    公开(公告)日：2010-06-29

    申请号：US11416850

    申请日：2006-05-02

    申请人： Loren J. Wise ,  Thomas W. Andre ,  Mark A. Durlam ,  Eric J. Salter

    发明人： Loren J. Wise ,  Thomas W. Andre ,  Mark A. Durlam ,  Eric J. Salter

    IPC分类号： G11C29/00

    CPC分类号： G11C29/52 ,  G06F11/1008 ,  G11C11/16

    摘要： A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits (104) is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit (104) is toggled back to its original state.

    摘要翻译： 诸如MRAM设备的存储器件包括与一组阵列位（102）相关联的自修复参考位（104）。 存储器执行错误检测步骤（例如，使用纠错编码（ECC）算法）来检测数据位内的一组错误的存在，其中一个参考位（104）被切换到不同的状态，如果 错误计数大于预定阈值，如果随后读取的错误集合保持不变，则将参考位（104）切换回其初始状态。

    MRAM architecture with electrically isolated read and write circuitry
    2.
    发明授权
    MRAM architecture with electrically isolated read and write circuitry 有权
    具有电隔离读写电路的MRAM架构

    公开(公告)号：US07154772B2

    公开(公告)日：2006-12-26

    申请号：US11076523

    申请日：2005-03-09

    申请人： Joseph J. Nahas ,  Thomas W. Andre ,  Chitra K. Subramanian ,  Bradley J. Garni ,  Mark A. Durlam

    发明人： Joseph J. Nahas ,  Thomas W. Andre ,  Chitra K. Subramanian ,  Bradley J. Garni ,  Mark A. Durlam

    IPC分类号： G11C11/00

    CPC分类号： G11C11/16

    摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.

    摘要翻译： 磁阻随机存取存储器（MRAM）具有单独的读写路径。 这通过不需要在特定线路上的读取和写入功能之间切换来减少外围电路。 通过具有专用于读取信号或写入信号的路径，可以针对这些功能优化电压电平。 作为仅读取功能的一部分的选择晶体管可以是低电压型，因为它们不必接收写电路的相对较高的电压。 类似地，写入电压不必降低以适应低电压型晶体管。 整体存储器的大小保持有效小，同时提高性能。 存储器单元被分组，使得与组相邻耦合到公共全局位线，这减少了为降低存储器单元选择提供电容减小组方法所需的空间。

    MRAM and methods for reading the MRAM
    4.
    发明授权
    MRAM and methods for reading the MRAM 有权
    MRAM和读取MRAM的方法

    公开(公告)号：US06909631B2

    公开(公告)日：2005-06-21

    申请号：US10679134

    申请日：2003-10-02

    申请人： Mark A. Durlam ,  Thomas W. Andre ,  Mark F. DeHerrera ,  Bradley N. Engel ,  Bradley J. Garni ,  Joseph J. Nahas ,  Nicholas D. Rizzo ,  Saied Tehrani

    发明人： Mark A. Durlam ,  Thomas W. Andre ,  Mark F. DeHerrera ,  Bradley N. Engel ,  Bradley J. Garni ,  Joseph J. Nahas ,  Nicholas D. Rizzo ,  Saied Tehrani

    IPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/14

    CPC分类号： G11C11/16 ,  G11C11/15

    摘要： An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.

    摘要翻译： 提供了一种MRAM，其通过利用每个存储单元中的隔离或选择装置来最小化MRAM密度的限制。 另外，提供了用于读取MRAM的联动存储单元中的MTJ的方法。 该方法包括确定至少部分地与MRAM的联动存储器单元的电阻相关联的电气值。 切换联合存储器单元中的MTJ，并且在切换MTJ之后确定至少部分地与组合存储器单元的电阻相关联的第二电值。 一旦确定了切换之前和切换之后的电气值，则分析两个电气值之间的差异，以确定MTJ的值。

    MRAM architecture with electrically isolated read and write circuitry
    5.
    发明授权
    MRAM architecture with electrically isolated read and write circuitry 失效
    具有电隔离读写电路的MRAM架构

    公开(公告)号：US06903964B2

    公开(公告)日：2005-06-07

    申请号：US10185868

    申请日：2002-06-28

    申请人： Joseph J. Nahas ,  Thomas W. Andre ,  Chitra K. Subramanian ,  Bradley J. Garni ,  Mark A. Durlam

    发明人： Joseph J. Nahas ,  Thomas W. Andre ,  Chitra K. Subramanian ,  Bradley J. Garni ,  Mark A. Durlam

    IPC分类号： G11C11/16 ,  G11C11/00

    CPC分类号： G11C11/16

    摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.

    摘要翻译： 磁阻随机存取存储器（MRAM）具有单独的读写路径。 这通过不需要在特定线路上的读取和写入功能之间切换来减少外围电路。 通过具有专用于读取信号或写入信号的路径，可以针对这些功能优化电压电平。 作为仅读取功能的一部分的选择晶体管可以是低电压型，因为它们不必接收写电路的相对较高的电压。 类似地，写入电压不必降低以适应低电压型晶体管。 整体存储器的大小保持有效小，同时提高性能。 存储器单元被分组，使得与组相邻耦合到公共全局位线，这减少了为降低存储器单元选择提供电容减小组方法所需的空间。

    Non-volatile memory cell and methods thereof
    7.
    发明申请
    Non-volatile memory cell and methods thereof 有权
    非易失性存储单元及其方法

    公开(公告)号：US20070268741A1

    公开(公告)日：2007-11-22

    申请号：US11438541

    申请日：2006-05-22

    申请人： Thomas W. Andre

    发明人： Thomas W. Andre

    IPC分类号： G11C11/00

    CPC分类号： G11C11/15

    摘要： A non-volatile storage element disposed at an integrated circuit is disclosed. The storage element includes a first resistive element having a first magnetic tunnel junction (MTJ) element, a first node coupled to the first resistive element, a second resistive element having of a second MTJ element, a second node coupled to the second resistive element, a sense amplifier having a first input coupled to the first node, a second input coupled to the second node, and an output, and a first conductor disposed to conduct a first current to set the first resistive element to a first resistive value and the second resistive element to a second resistive value different from the first resistive value.

    摘要翻译： 公开了一种设置在集成电路上的非易失性存储元件。 存储元件包括具有第一磁性隧道结（MTJ）元件的第一电阻元件，耦合到第一电阻元件的第一节点，具有第二MTJ元件的第二电阻元件，耦合到第二电阻元件的第二节点， 感测放大器，其具有耦合到第一节点的第一输入端，耦合到第二节点的第二输入端和输出端，以及布置成传导第一电流以将第一电阻元件设置为第一电阻值的第一导体， 电阻元件到不同于第一电阻值的第二电阻值。

    Sense amplifier with multiple bits sharing a common reference
    8.
    发明授权
    Sense amplifier with multiple bits sharing a common reference 有权
    具有多个位的感应放大器共享一个共同的参考

    公开(公告)号：US07292484B1

    公开(公告)日：2007-11-06

    申请号：US11422774

    申请日：2006-06-07

    申请人： Thomas W. Andre ,  Brad J. Garni ,  Joseph J. Nahas

    发明人： Thomas W. Andre ,  Brad J. Garni ,  Joseph J. Nahas

    IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C7/06 ,  G11C7/02

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C11/1673

    摘要： A memory circuit includes a sense amplifier in which a single reference signal is compared to two data signals from two memory cells. The reference signal is generated from the combination of memory cells in opposite logic states. The data signal capacitance is matched to the reference signal capacitance. With reduced but matched capacitance both high speed and high sensitivity can be achieved.

    摘要翻译： 存储器电路包括读出放大器，其中单个参考信号与来自两个存储器单元的两个数据信号进行比较。 参考信号是以相反逻辑状态的存储单元的组合产生的。 数据信号电容与参考信号电容匹配。 通过降低但匹配的电容，可以实现高速度和高灵敏度。

    MRAM memory with residual write field reset
    9.
    发明授权
    MRAM memory with residual write field reset 失效
    MRAM存储器具有残留写入域复位

    公开(公告)号：US07206223B1

    公开(公告)日：2007-04-17

    申请号：US11297203

    申请日：2005-12-07

    申请人： Joseph J. Nahas ,  Thomas W. Andre ,  Chitra K. Subramanian ,  Nicholas David Rizzo

    发明人： Joseph J. Nahas ,  Thomas W. Andre ,  Chitra K. Subramanian ,  Nicholas David Rizzo

    IPC分类号： G11C11/00

    CPC分类号： G11C11/15

    摘要： A magnetoresistive random access memory (MRAM) (900) that is susceptible to a residual magnetic field is compensated during a write operation. A first magnetic field (208) is applied to a memory cell during a first time period, the first magnetic field having a first direction (y) and a first magnitude. A second magnetic field (212) is applied to the memory cell during a second time period and having a second direction (x) and a second magnitude. A third magnetic field (702) is applied to the memory cell during a third time period, wherein the third time period overlaps at least a portion of the second time period, the third magnetic field having a third direction (−y) which is approximately opposite to the first direction of the first magnetic field. Currents are selectively applied through conductors in the memory cell to apply the three magnetic fields.

    摘要翻译： 在写入操作期间补偿易受残余磁场影响的磁阻随机存取存储器（MRAM）（900）。 第一磁场（208）在第一时间周期内被施加到存储单元，第一磁场具有第一方向（y）和第一大小。 第二磁场（212）在第二时间段期间被施加到存储器单元并且具有第二方向（x）和第二大小。 在第三时间段期间，第三磁场（702）被施加到存储器单元，其中第三时间周期与第二时间段的至少一部分重叠，第三磁场具有近似的第三方向（-y） 与第一磁场的第一方向相反。 通过存储单元中的导体选择性地施加电流以施加三个磁场。

    Accelerated life test of MRAM cells
    10.
    发明授权
    Accelerated life test of MRAM cells 失效
    MRAM细胞加速寿命试验

    公开(公告)号：US06894937B2

    公开(公告)日：2005-05-17

    申请号：US10672959

    申请日：2003-09-26

    申请人： Bradley J. Garni ,  Thomas W. Andre ,  Joseph J. Nahas

    发明人： Bradley J. Garni ,  Thomas W. Andre ,  Joseph J. Nahas

    IPC分类号： G11C11/15 ,  G11C29/50 ,  G11C29/00

    CPC分类号： G11C29/50 ,  G11C11/16 ,  G11C2029/5002

    摘要： A circuit provides a stress voltage to magnetic tunnel junctions (MTJs), which comprise the storage elements of a magnetoresitive random access memory (MRAM), during an accelerated life test of the MRAM. The stress voltage is selected to provide a predetermined acceleration of aging compared to normal operation. A source follower circuit is used to apply a stress voltage to a subset of the memory cells at given point in time during the life test. The stress voltage is maintained at the desired voltage by a circuit that mocks the loading characteristics of the portion of the memory array being stressed. The result is a closely defined voltage applied to the MTJs so that the magnitude of the acceleration is well defined for all of the memory cells.

    摘要翻译： 在MRAM的加速寿命测试期间，电路向包括磁阻随机存取存储器（MRAM）的存储元件的磁隧道结（MTJ）提供应力电压。 选择应力电压以提供与正常操作相比预定的老化加速度。 源极跟随器电路用于在寿命测试期间的给定时间点将应力电压施加到存储器单元的子集。 应力电压通过嘲笑存储器阵列部分的负载特性受到应力的电路保持在所需电压。 结果是施加到MTJ的紧密定义的电压，使得对于所有存储器单元良好地限定加速度的大小。