摘要:
An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.
摘要:
An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.
摘要:
A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.
摘要:
A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.
摘要:
A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.
摘要:
A sense amplifier (10) develops internally a midpoint reference current from two reference bits. The midpoint reference current is used to sense the state of a memory bit having at least two distinct resistance states (H and L) by determining whether the sense memory bit develops a larger or smaller current. The midpoint reference current is developed within a single sense amplifier. Predetermined bias voltages are developed from each of a data bit cell, a reference cell programmed to a high state and a reference cell programmed to a low state. Currents are developed from the bias voltages and summed to create the midpoint reference current. A current differential amplifier senses whether the bit input has a high or low resistive state and outputs a voltage indicative of the sensed memory state.
摘要:
In a memory, a sensing system detects bit states using one data and two reference inputs, to sense a difference in conductance of a selected memory bit cell and a midpoint reference conductance. Reference conductance is generated as the average conductance of a memory cell in the high conductance state and a memory cell in the low conductance state. The data input is coupled to the selected memory bit cell. The two reference inputs are respectively coupled to memory cells in high and low conductance memory states. The sense amplifiers use either current biasing or voltage biasing to apply a sensing voltage within a predetermined voltage range across the bit cells. Capacitance coupled to complementary outputs of the sense amplifiers is balanced by the circuit designs. In one form, the two reference inputs are internally connected. One of several gain stages amplifies the sense amplifier output without injecting parasitic errors.
摘要:
A sense amplifier having three inputs determines the state of a memory bit cell by converting a bit input voltage, a high reference voltage, and a low reference voltage to respective current values. Current differences are formed between a bit current and a high reference current, and between a low reference current and a bit current. Current mirrors (154, 158 and 170, 166) and loads (160 and 168) are used in conjunction with current steering circuitry (150, 140, 142 and 162) to form the difference of the bit current and the high reference current and also form the difference of the low reference current and the bit current. Additionally, the sense amplifier drives differential outputs (OUT and OUT13B) to reflect the difference between the two current differential quantities.
摘要:
A memory (10, 60) having at least two resistance states is tested. In one form, the memory includes a first transistor (16, 68) having a current electrode coupled to a memory cell (14, 64) and a second transistor (26, 66) having a current electrode coupled to a reference memory cell (28, 74). The control electrode of the first transistor receives either a first reference voltage or a second reference voltage based on a test control signal, and the control electrode of a second transistor receives the first reference voltage. In a test mode, after the memory cell is programmed with a resistance state, the second reference voltage (different from the first reference voltage) is provided to the first transistor. The memory cell is then read to determine whether the memory can sense the previously programmed resistance state. In one embodiment, this test mode can be used to identify weak bits in the memory.
摘要:
In a memory, a bias circuit (112, 212, 312, 412) uses a current reference (108) for providing a reference current and control circuitry (106, 120) to bias a sense amplifier (114) with a varying voltage (VB). The varying voltage maintains current through MRAM bit cells (177-179) at a value proportional to the reference current over variations in average bit cell resistance with immunity to variations in process, supply voltage and temperature. In one form, a mock sense amplifier (122, 126, 132, 134) and mock array of bit cells (130, 136) are used to establish internal steady state voltages equivalent to a steady state condition of the sense amplifier with equalized outputs and to generate the varying bias voltage. Matching diode-connected transistors in each of the control circuitry and either the mock sense amplifier or the sense amplifier is used to generate the varying bias voltage.