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公开(公告)号：US20200152115A1
公开(公告)日：2020-05-14
申请号：US16183746
申请日：2018-11-08
Applicant: NOVATEK Microelectronics Corp.
Inventor： Chao-Kai Tu , Yueh-Hsun Tsai , Tzung-Yun Tsai , Kai-Yue Lin , Ying-Hsiang Wang
IPC: G09G3/20
Abstract: A source driver for a panel includes a plurality of driver cells. Each of the driver cells includes an output driver, a plurality of bias voltage generators and a selector. The output driver is configured to output a plurality of display data to the panel. The plurality of bias voltage generators is coupled to the output driver. Each of the bias voltage generators is configured to provide at least one bias voltage for the output driver. The selector, coupled to the output driver, is configured to select the bias voltage from one of the bias voltage generators to be provided for the output driver according to the plurality of display data.
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公开(公告)号：US08866529B2
公开(公告)日：2014-10-21
申请号：US13786589
申请日：2013-03-06
Applicant: Novatek Microelectronics Corp.
Inventor： Tse-Hung Wu , Chao-Kai Tu
CPC classification number: G05F3/08 , H03F3/45 , H03F2203/45061
Abstract: An interface circuit includes a receiver, a first terminal resistor, a second terminal resistor, a common mode capacitor, a first switch, a second switch, and a common mode potential adjustment circuit. The receiver includes a first channel for receiving a first channel voltage, and a second channel for receiving a second channel voltage. The common mode capacitor provides a common mode potential. The first switch electrically connects the first terminal resistor to the common mode capacitor, and the second switch electrically connects the second terminal resistor to the common mode capacitor. The common mode potential adjustment circuit is coupled to the first switch, the second switch and the common mode capacitor, and adjusts the common mode potential according to the first channel voltage and the second channel voltage.
Abstract translation: 接口电路包括接收器，第一端子电阻器，第二端子电阻器，共模电容器，第一开关，第二开关和共模电位调节电路。 接收机包括用于接收第一信道电压的第一信道和用于接收第二信道电压的第二信道。 共模电容提供共模电位。 第一开关将第一端子电阻器电连接到共模电容器，并且第二开关将第二端子电阻器电连接到共模电容器。 共模电位调节电路耦合到第一开关，第二开关和共模电容器，并根据第一通道电压和第二通道电压调节共模电位。
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公开(公告)号：US09780794B2
公开(公告)日：2017-10-03
申请号：US14644216
申请日：2015-03-11
Applicant: Novatek Microelectronics Corp.
Inventor： Chao-Kai Tu , Rong-Sing Chu
CPC classification number: H03L7/0807 , H03L7/0816 , H03L7/087 , H04L7/0037 , H04L7/0337
Abstract: A clock and data recovery apparatus which includes a voltage controlled delay line (VCDL), a phase detector (PD) and a control voltage generating circuit is provided. The VCDL generates a plurality of clock signals with different phases according to a reference clock signal and a control voltage. The PD detects the phase relationship between a first input signal and a second input signal, and produces a detection result. A data signal or one of the clock signals is used as the first input signal, and one or more of the clock signals is/are used as the second input signal. The control voltage generating circuit generates the control voltage to the VCDL according to the detection result of the PD.
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公开(公告)号：US20140097889A1
公开(公告)日：2014-04-10
申请号：US13786589
申请日：2013-03-06
Applicant: NOVATEK MICROELECTRONICS CORP.
Inventor： Tse-Hung WU , Chao-Kai Tu
IPC: G05F3/08
CPC classification number: G05F3/08 , H03F3/45 , H03F2203/45061
Abstract: An interface circuit includes a receiver, a first terminal resistor, a second terminal resistor, a common mode capacitor, a first switch, a second switch, and a common mode potential adjustment circuit. The receiver includes a first channel for receiving a first channel voltage, and a second channel for receiving a second channel voltage. The common mode capacitor provides a common mode potential. The first switch electrically connects the first terminal resistor to the common mode capacitor, and the second switch electrically connects the second terminal resistor to the common mode capacitor. The common mode potential adjustment circuit is coupled to the first switch, the second switch and the common mode capacitor, and adjusts the common mode potential according to the first channel voltage and the second channel voltage.
Abstract translation: 接口电路包括接收器，第一端子电阻器，第二端子电阻器，共模电容器，第一开关，第二开关和共模电位调节电路。 接收机包括用于接收第一信道电压的第一信道和用于接收第二信道电压的第二信道。 共模电容提供共模电位。 第一开关将第一端子电阻器电连接到共模电容器，并且第二开关将第二端子电阻器电连接到共模电容器。 共模电位调节电路耦合到第一开关，第二开关和共模电容器，并根据第一通道电压和第二通道电压调节共模电位。
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公开(公告)号：US20140198021A1
公开(公告)日：2014-07-17
申请号：US13939194
申请日：2013-07-11
Applicant: Novatek Microelectronics Corp.
Inventor： Chao-Kai Tu , Kuang-Feng Sung , Shun-Hsun Yang , Teng-Jui Yu
IPC: G09G3/36
CPC classification number: G09G3/3688 , G09G2310/0297 , G09G2360/18 , G09G2370/08
Abstract: A display driving apparatus, including an image processor, a timing controller, and a plurality of source drivers, is provided. The image processor determines whether an image frame corresponding to a frame data is a static image and outputs the frame data and a determination result. The timing controller receives the frame data from the image processor and outputs the frame data. The source drivers receive the frame data from the timing controller and drive a display panel according to the frame data. Each of the source drivers includes a memory module configured to store the frame data corresponding to the static image. When the source drivers drive the display panel according to the frame data corresponding to the static image, the image processor stops outputting the frame data to the timing controller, and the timing controller stops outputting the frame data to the source drivers.
Abstract translation: 提供了包括图像处理器，定时控制器和多个源驱动器的显示驱动装置。 图像处理器确定与帧数据相对应的图像帧是否是静态图像，并且输出帧数据和确定结果。 定时控制器从图像处理器接收帧数据并输出帧数据。 源驱动器从定时控制器接收帧数据，并根据帧数据驱动显示面板。 每个源驱动器包括被配置为存储对应于静态图像的帧数据的存储器模块。 当源驱动器根据对应于静态图像的帧数据驱动显示面板时，图像处理器停止向定时控制器输出帧数据，并且定时控制器停止向源驱动器输出帧数据。
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Patent Agency Ranking
公开(公告)号：US20140176227A1
公开(公告)日：2014-06-26
申请号：US13938225
申请日：2013-07-09
Applicant: Novatek Microelectronics Corp.
Inventor： Tse-Hung Wu , Chao-Kai Tu , Chia-Wei Su
IPC: H03K17/16
CPC classification number: H03K19/017509 , H03K17/162 , H03K2217/0054
Abstract: A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit.
Abstract translation: 数据控制电路包括输出级电路，开关电路和阻抗模块。 输出级电路输出数据信号。 开关电路的输入端耦合到输出级电路的输出端，开关电路的输出端耦合到后级电路。 根据控制信号的控制，开关电路确定是否将输出级电路的数据信号发送到后级电路。 阻抗模块配置在输出级电路中，配置在输出级电路和开关电路之间，或配置在开关电路中。 这里，阻抗模块减少从开关电路流向输出级电路的噪声。
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公开(公告)号：US11677594B1
公开(公告)日：2023-06-13
申请号：US17706632
申请日：2022-03-29
Applicant: Novatek Microelectronics Corp.
Inventor： Tien-Chien Lee , Chao-Kai Tu , Sheng Hao Tseng
CPC classification number: H04L25/0328 , H04L25/0272 , H04L25/061
Abstract: The disclosure provides a receiver and an automatic offset cancellation (AOC) method thereof. The receiver includes a receiving channel circuit and an AOC circuit. The receiving channel circuit generates an equalized differential signal including an equalized first-end signal and an equalized second-end signal according to an input differential signal. The AOC circuit detects a peak of the equalized first-end signal to generate a first peak detection result. The AOC circuit detects a peak of the equalized second-end signal to generate a second peak detection result. The AOC circuit compares the first peak detection result with the second peak detection result to generate a comparison result. The AOC circuit compensates a mismatch of an input differential pair in the receiving channel circuit according to the comparison result.
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公开(公告)号：US09537487B2
公开(公告)日：2017-01-03
申请号：US14582201
申请日：2014-12-24
Applicant: Novatek Microelectronics Corp.
Inventor： Tse-Hung Wu , Chao-Kai Tu , Chia-Wei Su
IPC: H03K19/0175 , H03K17/16
CPC classification number: H03K19/017509 , H03K17/162 , H03K2217/0054
Abstract: A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit.
Abstract translation: 数据控制电路包括输出级电路，开关电路和阻抗模块。 输出级电路输出数据信号。 开关电路的输入端耦合到输出级电路的输出端，开关电路的输出端耦合到后级电路。 根据控制信号的控制，开关电路确定是否将输出级电路的数据信号发送到后级电路。 阻抗模块配置在输出级电路中，配置在输出级电路和开关电路之间，或配置在开关电路中。 这里，阻抗模块减少从开关电路流向输出级电路的噪声。
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公开(公告)号：US20160043860A1
公开(公告)日：2016-02-11
申请号：US14644216
申请日：2015-03-11
Applicant: Novatek Microelectronics Corp.
Inventor： Chao-Kai Tu , Rong-Sing Chu
CPC classification number: H03L7/0807 , H03L7/0816 , H03L7/087 , H04L7/0037 , H04L7/0337
Abstract: A clock and data recovery apparatus which includes a voltage controlled delay line (VCDL), a phase detector (PD) and a control voltage generating circuit is provided. The VCDL generates a plurality of clock signals with different phases according to a reference clock signal and a control voltage. The PD detects the phase relationship between a first input signal and a second input signal, and produces a detection result. A data signal or one of the clock signals is used as the first input signal, and one or more of the clock signals is/are used as the second input signal. The control voltage generating circuit generates the control voltage to the VCDL according to the detection result of the PD.
Abstract translation: 提供了包括电压控制延迟线（VCDL），相位检测器（PD）和控制电压产生电路的时钟和数据恢复装置。 VCDL根据参考时钟信号和控制电压产生具有不同相位的多个时钟信号。 PD检测第一输入信号和第二输入信号之间的相位关系，并产生检测结果。 使用数据信号或时钟信号之一作为第一输入信号，并且使用一个或多个时钟信号作为第二输入信号。 控制电压产生电路根据PD的检测结果生成对VCDL的控制电压。
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公开(公告)号：US20150109027A1
公开(公告)日：2015-04-23
申请号：US14582201
申请日：2014-12-24
Applicant: Novatek Microelectronics Corp.
Inventor： Tse-Hung Wu , Chao-Kai Tu , Chia-Wei Su
IPC: H03K19/0175
CPC classification number: H03K19/017509 , H03K17/162 , H03K2217/0054
Abstract: A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit.
Abstract translation: 数据控制电路包括输出级电路，开关电路和阻抗模块。 输出级电路输出数据信号。 开关电路的输入端子耦合到输出级电路的输出端，开关电路的输出端耦合到后级电路。 根据控制信号的控制，开关电路确定是否将输出级电路的数据信号发送到后级电路。 阻抗模块配置在输出级电路中，配置在输出级电路和开关电路之间，或配置在开关电路中。 这里，阻抗模块减少从开关电路流向输出级电路的噪声。
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