公开(公告)号：US20210243101A1

公开(公告)日：2021-08-05

申请号：US16893327

申请日：2020-06-04

Applicant: NVIDIA CORPORATION

Inventor： Joohwan Kim ,  Benjamin Boudaoud ,  Josef B. Spjut ,  Morgan S. McGuire ,  Seth P. Schneider ,  Rouslan L. Dimitrov ,  Lars Nordskog ,  Cody J. Robson ,  Sau Yan Keith Li ,  Gerrit Ary Slavenburg ,  Tom J. Verbeure

IPC: H04L12/26 ,  G06T1/20 ,  G06F3/14 ,  G09G5/14

Abstract: A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.

公开(公告)号：US20220222783A1

公开(公告)日：2022-07-14

申请号：US17706473

申请日：2022-03-28

Applicant: NVIDIA Corporation

Inventor： Thomas Albert Petersen ,  Ankan Banerjee ,  Shishir Goyal ,  Sau Yan Keith Li ,  Lars Nordskog ,  Rouslan Dimitrov

IPC: G06T5/00 ,  G06T15/00 ,  G06F9/38 ,  G06T1/20 ,  G06T13/20 ,  G09G5/00 ,  G06T13/00

Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.

公开(公告)号：US11321816B2

公开(公告)日：2022-05-03

申请号：US17178078

申请日：2021-02-17

Applicant: NVIDIA Corporation

Inventor： Thomas Albert Petersen ,  Ankan Banerjee ,  Shishir Goyal ,  Sau Yan Keith Li ,  Lars Nordskog ,  Rouslan Dimitrov

IPC: G06T5/00 ,  G06T15/00 ,  G06F9/38 ,  G06T1/20 ,  G06T13/20 ,  G09G5/00 ,  G06T13/00

Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.

公开(公告)号：US20190172181A1

公开(公告)日：2019-06-06

申请号：US16208390

申请日：2018-12-03

Applicant: NVIDIA CORPORATION

Inventor： Thomas Albert Petersen ,  Ankan Banerjee ,  Shishir Goyal ,  Sau Yan Keith Li ,  Lars Nordskog ,  Rouslan Dimitrov

IPC: G06T5/00 ,  G06T15/00 ,  G06T13/20 ,  G06T1/20 ,  G06F9/38

Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.

公开(公告)号：US12056854B2

公开(公告)日：2024-08-06

申请号：US17706473

申请日：2022-03-28

Applicant: NVIDIA Corporation

Inventor： Thomas Albert Petersen ,  Ankan Banerjee ,  Shishir Goyal ,  Sau Yan Keith Li ,  Lars Nordskog ,  Rouslan Dimitrov

IPC: G06T5/70 ,  G06F9/38 ,  G06T1/20 ,  G06T13/00 ,  G06T13/20 ,  G06T15/00 ,  G09G5/00

CPC classification number: G06T5/70 ,  G06F9/3877 ,  G06T1/20 ,  G06T13/00 ,  G06T13/20 ,  G06T15/005 ,  G09G5/00

Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.

公开(公告)号：US20240202860A1

公开(公告)日：2024-06-20

申请号：US18594099

申请日：2024-03-04

Applicant: NVIDIA Corporation

Inventor： Sau Yan Keith Li ,  Seth Schneider ,  Cody Robson ,  Lars Nordskog ,  Charles Hansen ,  Rouslan Dimitrov

IPC: G06T1/20 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06T1/20 ,  G06F9/3836 ,  G06F9/4881

Abstract: A weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. The processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. A first largest weighted average execution time associated with one of the plurality of execution stages is determined. A delay to the initial execution stage prior to processing a first next frame is applied. The delay is determined based on the first largest weighted average execution time.

公开(公告)号：US11784906B2

公开(公告)日：2023-10-10

申请号：US16893327

申请日：2020-06-04

Applicant: NVIDIA CORPORATION

Inventor： Joohwan Kim ,  Benjamin Boudaoud ,  Josef B. Spjut ,  Morgan S. McGuire ,  Seth P. Schneider ,  Rouslan L. Dimitrov ,  Lars Nordskog ,  Cody J. Robson ,  Sau Yan Keith Li ,  Gerrit Ary Slavenburg ,  Tom J. Verbeure

IPC: H04L43/106 ,  H04L43/0852 ,  G06F3/14 ,  G09G5/14 ,  G06T1/20

CPC classification number: H04L43/106 ,  G06F3/14 ,  G06T1/20 ,  G09G5/14 ,  H04L43/0852 ,  G09G2340/0407

Abstract: A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.

公开(公告)号：US20180322682A1

公开(公告)日：2018-11-08

申请号：US15652109

申请日：2017-07-17

Applicant: NVIDIA CORPORATION

Inventor： Rouslan Dimitrov ,  Yury Uralsky ,  Lars Nordskog ,  Dmitriy Zhdan

IPC: G06T15/00 ,  G06F3/14 ,  G06T15/20

CPC classification number: G06T15/005 ,  G06F3/1431 ,  G09G5/395

Abstract: Techniques for rendering images on multiple tilted displays concurrently to mitigate perspective distortion are disclosed herein. According to one described approach, viewports are assigned to a center monitor and two peripheral monitors. Scene data for the viewports is calculated, and geometric primitives are generated for the viewports based on the scene data. Image transformation is performed based on a modified perspective value to modify geometry of the geometric primitives based on tilt angles of the displays, and the geometric primitives are rasterized using the modified geometry.

公开(公告)号：US11922533B2

公开(公告)日：2024-03-05

申请号：US17448258

申请日：2021-09-21

Applicant: NVIDIA Corporation

Inventor： Sau Yan Keith Li ,  Seth Schneider ,  Cody Robson ,  Lars Nordskog ,  Charles Hansen ,  Rouslan Dimitrov

IPC: G06T1/20 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06T1/20 ,  G06F9/3836 ,  G06F9/4881

Abstract: A weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. The processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. A first largest weighted average execution time associated with one of the plurality of execution stages is determined. A delay to the initial execution stage prior to processing a first next frame is applied. The delay is determined based on the first largest weighted average execution time.

公开(公告)号：US20230087268A1

公开(公告)日：2023-03-23

申请号：US17448258

申请日：2021-09-21

Applicant: NVIDIA Corporation

Inventor： Sau Yan Keith Li ,  Seth Schneider ,  Cody Robson ,  Lars Nordskog ,  Charles Hansen ,  Rouslan Dimitrov

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/38

Abstract: A weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. The processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. A first largest weighted average execution time associated with one of the plurality of execution stages is determined. A delay to the initial execution stage prior to processing a first next frame is applied. The delay is determined based on the first largest weighted average execution time.