公开(公告)号：US11238815B2

公开(公告)日：2022-02-01

申请号：US16271743

申请日：2019-02-08

Applicant: NVIDIA CORPORATION

Inventor： Tom J. Verbeure

IPC: G09G3/34 ,  G09G3/36 ,  G06F13/10 ,  G06F13/42 ,  G09G3/20

Abstract: A display controller within a display device includes a serial peripheral interface (SPI) that coordinates the updating of current settings for groups of light-emitting diodes (LEDs). The SPI controller operates in synchrony with a liquid-crystal display (LCD) vertical scan position in order to update the current settings for rows of LEDs in parallel with the updating of nearby rows of LCD pixels. When updating a row of LEDs, the SPI controller executes one or more SPI transactions included in an SPI program to write current settings for multiple LEDs nearly simultaneously. A compiler generates the SPI program based on the topology of LEDs included in the display device.

公开(公告)号：US10726797B2

公开(公告)日：2020-07-28

申请号：US16271744

申请日：2019-02-08

Applicant: NVIDIA CORPORATION

Inventor： Tom J. Verbeure

IPC: G09G3/34 ,  G09G3/36 ,  G06F13/10 ,  G06F13/42 ,  G09G3/20

Abstract: A display controller within a display device includes a serial peripheral interface (SPI) that coordinates the updating of current settings for groups of light-emitting diodes (LEDs). The SPI controller operates in synchrony with a liquid-crystal display (LCD) vertical scan position in order to update the current settings for rows of LEDs in parallel with the updating of nearby rows of LCD pixels. When updating a row of LEDs, the SPI controller executes one or more SPI transactions included in an SPI program to write current settings for multiple LEDs nearly simultaneously. A compiler generates the SPI program based on the topology of LEDs included in the display device.

公开(公告)号：US20210243101A1

公开(公告)日：2021-08-05

申请号：US16893327

申请日：2020-06-04

Applicant: NVIDIA CORPORATION

Inventor： Joohwan Kim ,  Benjamin Boudaoud ,  Josef B. Spjut ,  Morgan S. McGuire ,  Seth P. Schneider ,  Rouslan L. Dimitrov ,  Lars Nordskog ,  Cody J. Robson ,  Sau Yan Keith Li ,  Gerrit Ary Slavenburg ,  Tom J. Verbeure

IPC: H04L12/26 ,  G06T1/20 ,  G06F3/14 ,  G09G5/14

Abstract: A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.

公开(公告)号：US09563227B2

公开(公告)日：2017-02-07

申请号：US13761027

申请日：2013-02-06

Applicant: NVIDIA CORPORATION

Inventor： Tom J. Verbeure

IPC: G06F1/08 ,  H03L7/097

CPC classification number: G06F1/08 ,  H03L7/097

Abstract: A modulated clock device is provided that includes an update device for updating a phase of the modulated clock device. In one example, the update device includes an update phase multiplexer coupled to an output phase multiplexer of an output clock generator and configured to receive an input clock signal and one or more phases of the input clock signal; an output phase fractional counter coupled to the update phase multiplexer and configured to receive an update clock signal and to generate an output phase; and an update phase device coupled to the output phase fractional counter and to the update phase multiplexer. The output phase fractional counter is further configured to send the output phase to the output phase multiplexer and to the update phase device. The update phase device is configured to generate an update phase and to send the update phase to the update phase multiplexer.

Abstract translation: 提供了一种调制时钟装置，其包括用于更新调制时钟装置的相位的更新装置。 在一个示例中，更新装置包括耦合到输出时钟发生器的输出相位多路复用器并被配置为接收输入时钟信号和输入时钟信号的一个或多个相位的更新相位多路复用器; 耦合到更新相位多路复用器并被配置为接收更新时钟信号并产生输出相位的输出相位分数计数器; 以及耦合到输出相位分数计数器和更新相位多路复用器的更新相位装置。 输出相位分数计数器还被配置为将输出相位发送到输出相位多路复用器和更新相位装置。 更新相位装置被配置为生成更新阶段并将更新阶段发送到更新相位多路复用器。

公开(公告)号：US11784906B2

公开(公告)日：2023-10-10

申请号：US16893327

申请日：2020-06-04

Applicant: NVIDIA CORPORATION

Inventor： Joohwan Kim ,  Benjamin Boudaoud ,  Josef B. Spjut ,  Morgan S. McGuire ,  Seth P. Schneider ,  Rouslan L. Dimitrov ,  Lars Nordskog ,  Cody J. Robson ,  Sau Yan Keith Li ,  Gerrit Ary Slavenburg ,  Tom J. Verbeure

IPC: H04L43/106 ,  H04L43/0852 ,  G06F3/14 ,  G09G5/14 ,  G06T1/20

CPC classification number: H04L43/106 ,  G06F3/14 ,  G06T1/20 ,  G09G5/14 ,  H04L43/0852 ,  G09G2340/0407

Abstract: A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.

公开(公告)号：US11043172B2

公开(公告)日：2021-06-22

申请号：US16268438

申请日：2019-02-05

Applicant: NVIDIA CORPORATION

Inventor： Gerrit Ary Slavenburg ,  Robert Jan Schutten ,  Jens Roever ,  Tom J. Verbeure

IPC: G09G3/36 ,  G09G3/34

Abstract: A display controller progressively updates LEDs and LCD pixels in scanline order as portions of an image are scanned into a frame buffer. The display controller analyzes a first portion of the image that includes a first pixel value associated with a first LCD pixel. The display controller identifies a first LED that contributes luminance to the first LCD pixel and determines an LED current setting for the LED based on the first pixel value. The display controller then identifies a second LCD pixel that resides above the first LED and is associated with a second pixel value. The display controller configures the second LCD pixel based on the second pixel value and luminance contributions received at the second LCD pixel. Accordingly, the display controller need not wait for the entire image to be scanned into the frame buffer before initiating display of the image.

公开(公告)号：US11030968B2

公开(公告)日：2021-06-08

申请号：US16844126

申请日：2020-04-09

Applicant: NVIDIA Corporation

Inventor： Gerrit Slavenburg ,  Tom J. Verbeure

IPC: G09G5/00 ,  G09G3/36

Abstract: In various examples, images rendered by a processor—such as a graphics processing unit (GPU)—may be scanned out of memory in a middle-out scan order. Various architectures for liquid crystal displays (LCDs) may be implemented to support middle-out scanning, such as dual-panel architectures, ping-pong architectures, and architectures that support both top-down scan order and middle-out scan order. As a result, display latency within the system may be reduced, thereby increasing performance of the system—especially for high-performance applications such as gaming.

公开(公告)号：US20200243033A1

公开(公告)日：2020-07-30

申请号：US16844126

申请日：2020-04-09

Applicant: NVIDIA Corporation

Inventor： Gerrit Slavenburg ,  Tom J. Verbeure

IPC: G09G3/36

Abstract: In various examples, images rendered by a processor—such as a graphics processing unit (GPU)—may be scanned out of memory in a middle-out scan order. Various architectures for liquid crystal displays (LCDs) may be implemented to support middle-out scanning, such as dual-panel architectures, ping-pong architectures, and architectures that support both top-down scan order and middle-out scan order. As a result, display latency within the system may be reduced, thereby increasing performance of the system—especially for high-performance applications such as gaming.

公开(公告)号：US08994640B2

公开(公告)日：2015-03-31

申请号：US13828355

申请日：2013-03-14

Applicant: NVIDIA Corporation

Inventor： Gerrit Ary Slavenburg ,  Tom J. Verbeure ,  Robert Jan Schutten

IPC: G09G3/36 ,  G06F3/147 ,  G09G3/34 ,  G09G5/36

CPC classification number: G09G3/36 ,  G06F3/147 ,  G09G3/3406 ,  G09G3/3648 ,  G09G5/363 ,  G09G2310/0237 ,  G09G2320/0252 ,  G09G2320/0261 ,  G09G2320/0646 ,  G09G2340/16

Abstract: One embodiment of the present invention sets forth a technique for reducing motion blur in a liquid crystal display (LCD) by pulsing each frame with a relatively short pulse of backlight illumination while driving pixels within the LCD with compensated intensity values to account for LCD settling time and vertical position. An LCD drive compensation unit implements the disclosed technique to generate an intensity value for each pixel that is scanned into the LCD. The technique advantageously reduces motion blur while preserving uniform vertical display accuracy.

Abstract translation: 本发明的一个实施例提出了一种用于通过以相对较短的背光照明脉冲脉冲每个帧来减少液晶显示器（LCD）中的运动模糊的技术，同时以补偿的强度值驱动LCD内的像素以解决LCD建立时间 和垂直位置。 LCD驱动器补偿单元实现所公开的技术以产生扫描到LCD中的每个像素的强度值。 该技术有利地减少运动模糊，同时保持均匀的垂直显示精度。