公开(公告)号：US20170012628A1

公开(公告)日：2017-01-12

申请号：US14794411

申请日：2015-07-08

Applicant: NXP B.V.

Inventor： Kristof Blutman ,  Ajay Kapoor ,  Jose Pineda de Gyvez ,  Arnoud van der Wel

IPC: H03K19/0185

CPC classification number: H03K19/018514 ,  H03K3/356182 ,  H03K5/13 ,  H03K19/0185

Abstract: Aspects of the disclosure are directed to communications between respective power domains (circuitry) that may operate in a stacked arrangement in which the each domain operates over a different voltage range. A first circuit provides differential outputs that vary between first and second voltage levels, based on transitions of an input signal received from a first one of the power domains. First and second driver circuits are respectively coupled to the first and second differential outputs. A third driver circuit operates with the first and second circuits to level-shift the input signal from the first power domain to an output signal on a second power domain by driving an output circuit at the second voltage level in response to the input signal being at the first voltage level, and driving the output circuit at a third voltage level in response to the input signal being at the second voltage level.

Abstract translation: 本公开的方面涉及可以在每个域在不同电压范围上操作的堆叠布置中操作的相应功率域（电路）之间的通信。 第一电路提供基于从第一功率域接收的输入信号的转变而在第一和第二电压电平之间变化的差分输出。 第一和第二驱动器电路分别耦合到第一和第二差分输出。 第三驱动器电路与第一和第二电路一起工作，以响应于输入信号处于第二电压电平，通过驱动处于第二电压电平的输出电路来将输入信号从第一功率域电平移位到第二电源域上的输出信号 第一电压电平，并且响应于输入信号处于第二电压电平，将输出电路驱动在第三电压电平。

公开(公告)号：US09329609B1

公开(公告)日：2016-05-03

申请号：US14661151

申请日：2015-03-18

Applicant: NXP B.V.

Inventor： Shishir Goyal ,  Arnoud van der Wel

IPC: H03K5/22 ,  G05F1/46

CPC classification number: G05F1/46

Abstract: Disclosed is a differential driver circuit including an input module to receive an input signal and split the input signal into high and low components, a first level shifter to receive the high signal component and output a high side input signal to a high side driver, a delay module to receive the low signal component and output a low side input signal to a low side driver, and a multi-voltage domain phase detector to measure a phase difference between the high side input signal and the low side input signal to provide feedback to the input module and output a phase adjusted output signal to match a first delay timing of the first level shifter.

Abstract translation: 公开了一种差分驱动器电路，其包括用于接收输入信号并将输入信号分为高和低分量的输入模块，用于接收高信号分量并将高侧输入信号输出到高侧驱动器的第一电平移位器， 延迟模块接收低信号分量并向低侧驱动器输出低侧输入信号;以及多电压域相位检测器，用于测量高侧输入信号和低侧输入信号之间的相位差，以提供反馈 所述输入模块输出相位调整的输出信号以匹配所述第一电平移位器的第一延迟定时。

公开(公告)号：US20160079970A1

公开(公告)日：2016-03-17

申请号：US14484129

申请日：2014-09-11

Applicant: NXP B.V.

Inventor： Arnoud van der Wel

IPC: H03K5/02

CPC classification number: H03K5/02 ,  H01C13/02 ,  H01L23/647 ,  H01L27/0802 ,  H01L2924/0002 ,  H03H7/24 ,  H03H7/425 ,  H01L2924/00

Abstract: A resistive divider circuit for differential signaling is disclosed. The resistive divider includes a first branch and a second branch and each branch has an input, a first resistive component comprised of a number of unit resistors, a second resistive component comprised of a number of unit resistors, and an output connected between the first resistive component and the second resistive component, the output forming a differential mode output. The first resistive component and the second resistive component are comprised of an equal number of unit resistors.

Abstract translation: 公开了用于差分信号的电阻分压电路。 电阻分压器包括第一分支和第二分支，每个分支具有输入，由多个单位电阻组成的第一电阻分量，由多个单位电阻组成的第二电阻分量，以及连接在第一电阻 分量和第二电阻分量，输出形成差模输出。 第一电阻分量和第二电阻分量由等量的单位电阻组成。

公开(公告)号：US09917588B2

公开(公告)日：2018-03-13

申请号：US14794411

申请日：2015-07-08

Applicant: NXP B.V.

Inventor： Kristof Blutman ,  Ajay Kapoor ,  Jose Pineda de Gyvez ,  Arnoud van der Wel

IPC: H03L5/00 ,  H03K19/0185 ,  H03K5/13

CPC classification number: H03K19/018514 ,  H03K3/356182 ,  H03K5/13 ,  H03K19/0185

Abstract: Aspects of the disclosure are directed to communications between respective power domains (circuitry) that may operate in a stacked arrangement in which the each domain operates over a different voltage range. A first circuit provides differential outputs that vary between first and second voltage levels, based on transitions of an input signal received from a first one of the power domains. First and second driver circuits are respectively coupled to the first and second differential outputs. A third driver circuit operates with the first and second circuits to level-shift the input signal from the first power domain to an output signal on a second power domain by driving an output circuit at the second voltage level in response to the input signal being at the first voltage level, and driving the output circuit at a third voltage level in response to the input signal being at the second voltage level.

公开(公告)号：US09912335B2

公开(公告)日：2018-03-06

申请号：US14794485

申请日：2015-07-08

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Kristof Blutman ,  Jose Pineda de Gyvez ,  Arnoud van der Wel

IPC: H03L5/00 ,  H03K19/0185 ,  G06F1/32 ,  H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/018507 ,  G06F1/3234 ,  H03K19/0019 ,  H03K19/0175

Abstract: Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication).

公开(公告)号：US20170012627A1

公开(公告)日：2017-01-12

申请号：US14794485

申请日：2015-07-08

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Kristof Blutman ,  Jose Pineda de Gyvez ,  Arnoud van der Wel

IPC: H03K19/0185

CPC classification number: H03K19/018507 ,  G06F1/3234 ,  H03K19/0019 ,  H03K19/0175

Abstract: Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication).

Abstract translation: 本公开的方面涉及通过各个电路之间的通信的电平转换方法。 如可以根据本文特征的一个或多个实施例来实现的，在各个电路之间通过的通信的电压电平被选择性地移位。 在各个电路在相对于彼此在电压范围内移位的相应功率域下工作时，通信的电压电平发生偏移。 例如，该方法可以有助于对于其中提供一个电路的低电平电压作为另一个电路的高电平电压的堆叠电路的功率节省。 当各个电路在公共功率域下工作时，通信直接在相应的电路之间传递（例如，绕过任何电平转换，并促进快速通信）。

公开(公告)号：US09413342B2

公开(公告)日：2016-08-09

申请号：US14484129

申请日：2014-09-11

Applicant: NXP B.V.

Inventor： Arnoud van der Wel

IPC: H03K5/02 ,  H01C13/02 ,  H03H7/24 ,  H01L23/64 ,  H01L27/08 ,  H03H7/42

CPC classification number: H03K5/02 ,  H01C13/02 ,  H01L23/647 ,  H01L27/0802 ,  H01L2924/0002 ,  H03H7/24 ,  H03H7/425 ,  H01L2924/00

Abstract: A resistive divider circuit for differential signaling is disclosed. The resistive divider includes a first branch and a second branch and each branch has an input, a first resistive component comprised of a number of unit resistors, a second resistive component comprised of a number of unit resistors, and an output connected between the first resistive component and the second resistive component, the output forming a differential mode output. The first resistive component and the second resistive component are comprised of an equal number of unit resistors.

Abstract translation: 公开了用于差分信号的电阻分压电路。 电阻分压器包括第一分支和第二分支，每个分支具有输入，由多个单位电阻组成的第一电阻分量，由多个单位电阻组成的第二电阻分量，以及连接在第一电阻 分量和第二电阻分量，输出形成差模输出。 第一电阻分量和第二电阻分量由等量的单位电阻组成。