公开(公告)号：US20250046651A1

公开(公告)日：2025-02-06

申请号：US18228934

申请日：2023-08-01

Applicant: NXP B.V.

Inventor： Saumitra Raj Mehrotra ,  Gerben Boon ,  Gerrit Willem Nijland ,  James Gordon Boyd ,  Ronghua Zhu ,  Todd Roggenbauer

IPC: H01L21/765 ,  H01L23/52

Abstract: A method and apparatus are disclosed for an integrated circuit having a high voltage tub including a buried layer of a first conductivity type formed in a substrate of a second conductivity type, a central region of the first conductivity type formed in the substrate in contact with the buried layer, a first floating isolation trench formed in the substrate to surround the central region and to extend down to and surround the buried layer, a second floating isolation trench formed in the substrate around the first isolation trench, a shallow ring region of the first conductivity type formed in the substrate between the first floating isolation trench and the second floating isolation trench, a first conductive interconnect structure for electrically shorting the central region to the shallow ring region, and a second conductive interconnect structure for electrically shorting the first floating isolation trench to the second floating isolation trench.

公开(公告)号：US20220293771A1

公开(公告)日：2022-09-15

申请号：US17199153

申请日：2021-03-11

Applicant: NXP B.V.

Inventor： Xin Lin ,  Ronghua Zhu ,  Zhihong Zhang ,  Yujing Wu ,  Pete Rodriquez

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed, wherein the drain electrode is separated from a first location of the plate structure by a first distance along a central axis of an active area of the semiconductor device in a direction of a current flow between a source and a drain of the semiconductor device, the drain electrode is separated from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

公开(公告)号：US10825717B1

公开(公告)日：2020-11-03

申请号：US16505994

申请日：2019-07-09

Applicant: NXP B.V.

Inventor： Ronghua Zhu ,  Eric Ooms ,  Xin Lin

IPC: H01L21/762 ,  H01L21/311 ,  H01L29/40 ,  H01L29/78

Abstract: A method for reducing transistor sensitivity to shallow trench isolation defects (STI) includes filling a trench formed in a substrate of a semiconductor device, at least partially, with a first oxide, the trench defines an STI and includes a defect extending from the substrate. A mask defines a planar area within the isolation region including a first lateral distance between an edge of the mask and an edge of the isolation region. The first oxide is at least partially removed beneath the planar area with an oxide etch to expose a top portion of the defect. The top portion of the defect is removed with a semiconductor etch. After removing the top portion of the defect, the trench is at least partially filled with a second oxide. A field plate of a split-gate transistor is formed over the STI.

公开(公告)号：US10418483B2

公开(公告)日：2019-09-17

申请号：US15797450

申请日：2017-10-30

Applicant: NXP B.V.

Inventor： Bernhard Grote ,  Xin Lin ,  Saumitra Raj Mehrotra ,  Ljubo Radic ,  Ronghua Zhu

IPC: H01L21/761 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L29/36 ,  H01L29/08 ,  H01L29/49 ,  H01L29/40

Abstract: An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.

公开(公告)号：US11610978B2

公开(公告)日：2023-03-21

申请号：US17199153

申请日：2021-03-11

Applicant: NXP B.V.

Inventor： Xin Lin ,  Ronghua Zhu ,  Zhihong Zhang ,  Yujing Wu ,  Pete Rodriquez

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/762 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L27/02 ,  H01L29/786

Abstract: A method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed, wherein the drain electrode is separated from a first location of the plate structure by a first distance along a central axis of an active area of the semiconductor device in a direction of a current flow between a source and a drain of the semiconductor device, the drain electrode is separated from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

公开(公告)号：US20180151723A1

公开(公告)日：2018-05-31

申请号：US15797450

申请日：2017-10-30

Applicant: NXP B.V.

Inventor： Bernhard Grote ,  Xin Lin ,  Saumitra Raj Mehrotra ,  Ljubo Radic ,  Ronghua Zhu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/36 ,  H01L29/66 ,  H01L21/761 ,  H01L21/265

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/402 ,  H01L29/4916 ,  H01L29/66681 ,  H01L29/7835

Abstract: An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.

公开(公告)号：US20240128316A1

公开(公告)日：2024-04-18

申请号：US18473950

申请日：2023-09-25

Applicant: NXP B.V.

Inventor： Saumitra Raj Mehrotra ,  Ronghua Zhu ,  Todd Roggenbauer

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L29/0623

Abstract: A semiconductor device comprising a substrate having a first conductivity type, the substrate having a top surface and a bottom surface, a first buried layer disposed in the substrate at a first depth from the top surface, wherein the first buried layer has a second conductivity type and a first doping concentration, a second buried layer adjacent and surrounding the first buried layer at the first depth, wherein the second buried layer has the second conductivity type and a second doping concentration, wherein the second doping concentration is less than the first doping concentration, and an isolation trench disposed in the substrate and surrounding the second buried layer, wherein the isolation trench extends from the top surface of the substrate to a second depth, the second depth exceeding the first depth.