公开(公告)号：US10230638B2

公开(公告)日：2019-03-12

申请号：US16042339

申请日：2018-07-23

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/741 ,  H04L29/06

Abstract: An integrated circuit includes a processor and an exact-match flow table structure. A first packet is received onto the integrated circuit. The packet is determined to be of a first type. As a result of this determination, execution by the processor of a first sequence of instructions is initiated. This execution causes bits of the first packet to be concatenated and modified in a first way, thereby generating a first Flow Id. The first Flow Id is an exact-match for the Flow Id of a first stored flow entry. A second packet is received. It is of a first type. As a result, a second sequence of instructions is executed. This causes bits of the second packet to be concatenated and modified in a second way, thereby generating a second Flow Id. The second Flow Id is an exact-match for the Flow Id of a second stored flow entry.

公开(公告)号：US10031878B2

公开(公告)日：2018-07-24

申请号：US15463857

申请日：2017-03-20

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F13/14 ,  G06F13/40 ,  G06F13/36

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. A configurable mesh data bus includes a command mesh, a pull-id mesh, and two data meshes. The configurable mesh data bus extends through all the islands. For each mesh, each island includes a centrally located crossbar switch and eight half links. Two half links extend to ports on the top edge of the island, a half link extends to a port on a right edge of the island, two half links extend to ports on the bottom edge of the island, and a half link extents to a port on the left edge of the island. Two additional links extend to functional circuitry of the island. The configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit.

公开(公告)号：US09899996B1

公开(公告)日：2018-02-20

申请号：US14556135

申请日：2014-11-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Bruce A. Wilford

IPC: G06F7/02 ,  H03K17/00 ,  G06F9/46 ,  G06F13/40

CPC classification number: H03K17/00 ,  G06F9/467 ,  G06F13/40 ,  H04L45/745 ,  H04L45/748

Abstract: A hardware trie structure includes a tree of internal node circuits and leaf node circuits. Each internal node is configured by a corresponding multi-bit node control value (NCV). Each leaf node can output a corresponding result value (RV). An input value (IV) supplied onto input leads of the trie causes signals to propagate through the trie such that one of the leaf nodes outputs one of the RVs onto output leads of the trie. In a transactional memory, a memory stores a set of NCVs and RVs. In response to a lookup command, the NCVs and RVs are read out of memory and are used to configure the trie. The IV of the lookup is supplied to the input leads, and the trie looks up an RV. A non-final RV initiates another lookup in a recursive fashion, whereas a final RV is returned as the result of the lookup command.

公开(公告)号：US20170357594A1

公开(公告)日：2017-12-14

申请号：US15688937

申请日：2017-08-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Rolf Neugebauer

IPC: G06F12/109 ,  G06F9/46 ,  G06F13/38 ,  G06F12/1081

CPC classification number: G06F9/467 ,  G06F12/1081 ,  G06F12/109 ,  G06F13/385 ,  G06F2212/657 ,  G06F2213/0026

Abstract: A transactional memory receives a command, where the command includes an address and a novel GAA (Generate Alert On Action) bit. If the GAA bit is set and if the transactional memory is enabled to generate alerts and if the command is a write into a memory of the transactional memory, then the transactional memory outputs an alert in accordance with preconfigured parameters. For example, the alert may be preconfigured to carry a value or key usable by the recipient of the alert to determine the reason for the alert. The alert may be set up to include the address of the memory location in the transactional memory that was written. The transactional memory may be set up to send the alert to a predetermined destination. The outputting of the alert may be a writing of information into a predetermined destination, or may be an outputting of an interrupt signal.

公开(公告)号：US09819585B1

公开(公告)日：2017-11-14

申请号：US14726428

申请日：2015-05-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/701 ,  H04L12/741 ,  H04L29/06

CPC classification number: H04L45/745 ,  H04L49/00 ,  H04L69/22

Abstract: An exact-match flow table structure stores flow entries. Each flow entry includes a Flow Id. A flow entry is generated from an incoming packet. The flow table structure determines whether there is a stored flow entry, the Flow Id of which is an exact-match for the generated Flow Id. In one novel aspect, a programmable reduce table circuit is used to generate a Flow Id. A selected subset of bits of an incoming packet is supplied as an address to an SRAM, so that the SRAM outputs a data value. The data value is supplied to a programmable lookup circuit such that the lookup circuit performs a selected type of lookup operation, and outputs a result value of a reduced number of bits. A multiplexer circuit is used to form a Flow Id such that the result value is a part of the Flow Id.

公开(公告)号：US09807006B1

公开(公告)日：2017-10-31

申请号：US14726433

申请日：2015-05-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/741 ,  H04L29/06 ,  H04L12/801 ,  H04L12/933 ,  H04L5/00

CPC classification number: H04L45/745 ,  H04L5/0044 ,  H04L47/10 ,  H04L49/101 ,  H04L69/22

Abstract: An integrated circuit includes an exact-match flow table structure, a crossbar switch, and an egress packet modifier. Each flow entry includes an egress action value, an egress flow number, and an egress port number. A Flow Id is generated from an incoming packet. The Flow Id is used to obtain a matching flow entry. A portion of the packet is communicated across the crossbar switch to the egress packet modifier, along with the egress action value and flow number. The egress action value is used to obtain non-flow specific header information stored in a first egress memory. The egress flow number is used to obtain flow specific header information stored in a second egress memory. The egress packet modifier adds the header information onto the portion of the packet, thereby generating a complete packet. The complete packet is then output from an egress port indicated by the egress port number.

公开(公告)号：US09753883B2

公开(公告)日：2017-09-05

申请号：US14172844

申请日：2014-02-04

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Rolf Neugebauer

IPC: G06F12/10 ,  G06F13/42 ,  H04L12/741 ,  G06F9/455 ,  G06F21/53 ,  G06F21/85

CPC classification number: G06F13/4234 ,  G06F9/45558 ,  G06F12/10 ,  G06F21/53 ,  G06F21/85 ,  G06F2009/45595 ,  H04L45/74

Abstract: A Network Interface Device (NID) of a web hosting server implements multiple virtual NIDs. A virtual NID is configured by configuration information in an appropriate one of a set of smaller blocks in a high-speed memory on the NID. There is a smaller block for each virtual NID. A virtual machine on the host can configure its virtual NID by writing configuration information into a larger block in PCIe address space. Circuitry on the NID detects that the PCIe write is into address space occupied by the larger blocks. If the write is into this space, then address translation circuitry converts the PCIe address into a smaller address that maps to the appropriate one of the smaller blocks associated with the virtual NID to be configured. If the PCIe write is detected not to be an access of a larger block, then the NID does not perform the address translation.

公开(公告)号：US09753710B2

公开(公告)日：2017-09-05

申请号：US14074632

申请日：2013-11-07

Applicant: Netronome Systems, Inc.

Inventor： Espen Skoglund ,  Rolf Neugebauer ,  Francois Henri Theron ,  Gavin J. Stark

IPC: G06F9/445 ,  G06F9/45

CPC classification number: G06F8/54 ,  G06F8/447

Abstract: A source code symbol can be declared to have a scope level indicative of a level in a hierarchy of scope levels, where the scope level indicates a circuit level or a sub-circuit level in the hierarchy. A novel instruction to the linker can define the symbol to be of a desired scope level. Location information indicates where different amounts of the object code are to be loaded into a system. A novel linker program uses the location information, along with the scope level information of the symbol, to uniquify instances of the symbol if necessary to resolve name collisions of symbols having the same scope. After the symbol uniquification step, the linker performs resource allocation. A resource instance is allocated to each symbol. The linker then replaces each instance of the symbol in the object code with the address of the allocated resource instance, thereby generating executable code.

公开(公告)号：US09612841B1

公开(公告)日：2017-04-04

申请号：US14530765

申请日：2014-11-02

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3887 ,  G06F9/30047 ,  G06F9/30069 ,  G06F9/383 ,  G06F9/46

Abstract: A multi-processor includes a pool of processors and a common packet buffer memory. Bytes of packet data of a packet are stored in the packet buffer memory. Each of the processors has an intelligent packet data register file. One processor is tasked with processing the packet data, and its packet data register file caches a subset of the bytes. Some instructions when executed require that the packet data register file supply the processor execute stage with certain bytes of the packet data. The register file includes a set of slice portions, where each slice portion is responsible for different bytes of the overall packet data. Each slice portion independently handles stalling the processor and prefetching any bytes it is responsible for. The slice portions output their bytes in a shifted and masked fashion to that the overall register file output is properly presented to the execute stage.

公开(公告)号：US09558224B2

公开(公告)日：2017-01-31

申请号：US14151643

申请日：2014-01-09

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F17/30

CPC classification number: G06F17/30339 ,  G06F17/30985

Abstract: An automaton hardware engine employs a transition table organized into 2n rows, where each row comprises a plurality of n-bit storage locations, and where each storage location can store at most one n-bit entry value. Each row corresponds to an automaton state. In one example, at least two NFAs are encoded into the table. The first NFA is indexed into the rows of the transition table in a first way, and the second NFA is indexed in to the rows of the transition table in a second way. Due to this indexing, all rows are usable to store entry values that point to other rows.

Abstract translation: 自动机硬件引擎采用组织成2n行的转换表，其中每行包括多个n位存储位置，并且其中每个存储位置最多可以存储一个n位输入值。 每行对应于自动机状态。 在一个示例中，至少两个NFA被编码到表中。 第一个NFA以第一种方式索引到转换表的行中，第二个NFA以第二种方式索引到转换表的行中。 由于此索引，所有行都可用于存储指向其他行的条目值。