公开(公告)号：US09515946B2

公开(公告)日：2016-12-06

申请号：US14321756

申请日：2014-07-01

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb

IPC: H04L12/28 ,  H04L12/863

CPC classification number: H04L47/622

Abstract: Incoming frame data is stored in a plurality of dual linked lists of buffers in a pipelined memory. The dual linked lists of buffers are maintained by a link manager. The link manager maintains, for each dual linked list of buffers, a first head pointer, a second head pointer, a first tail pointer, a second tail pointer, a head pointer active bit, and a tail pointer active bit. The first head and tail pointers are used to maintain the first linked list of the dual linked list. The second head and tail pointers are used to maintain the second linked list of the dual linked list. Due to the pipelined nature of the memory, the dual linked list system can be popped to supply dequeued values at a sustained rate of more than one value per the read access latency time of the pipelined memory.

Abstract translation: 输入帧数据被存储在流水线存储器中的多个缓冲器的双链表中。 缓冲区的双链表由链接管理器维护。 链路管理器针对缓冲器的每个双链表维护第一头指针，第二头指针，第一尾指针，第二尾指针，头指针活动位和尾指针有效位。 第一个头和尾指针用于维护双链表的第一个链表。 第二个头尾指针用于维护双链表的第二个链表。 由于存储器的流水线性质，可以弹出双链表系统以便以流水线存储器的读取访问等待时间为单位以多于一个值的持续速率提供出队值。

公开(公告)号：US09258256B2

公开(公告)日：2016-02-09

申请号：US14321762

申请日：2014-07-01

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb

IPC: G06F13/00 ,  G06F13/18 ,  G06F13/362 ,  H04L12/70 ,  H04L12/931 ,  H04L12/861 ,  H04L12/947

CPC classification number: H04L49/3045 ,  H04L49/9005 ,  H04L49/9042 ,  Y02P80/112

Abstract: An overflow threshold value is stored for each of a plurality of virtual channels. A link manager maintains, for each virtual channel, a buffer count. If the buffer count for a virtual channel is detected to exceed the overflow threshold value for a virtual channel whose originating PCP flows were merged, then a PFC (Priority Flow Control) pause frame is generated where multiple ones of the priority class enable bits are set to indicate that multiple PCP flows should be paused. For the particular virtual channel that is overloaded, an Inverse PCP Remap LUT (IPRLUT) circuit performs inverse PCP mapping, including merging and/or reordering mapping, and outputs an indication of each of those PCP flows that is associated with the overloaded virtual channel. Associated physical MAC port circuitry uses this information to generate the PFC pause frame so that the appropriate multiple enable bits are set in the pause frame.

Abstract translation: 为多个虚拟通道中的每一个存储溢出阈值。 链路管理器为每个虚拟通道维护缓冲区计数。 如果检测到虚拟通道的缓冲器计数超过其始发PCP流合并的虚拟通道的溢出阈值，则生成PFC（优先级流控制）暂停帧，其中设置了多个优先级使能位 以指示应暂停多个PCP流。 对于重载的特定虚拟信道，反PCP重映射LUT（IPRLUT）电路执行反PCP映射，包括合并和/或重新排序映射，并且输出与重载虚拟信道相关联的每个PCP流的指示。 相关的物理MAC端口电路使用该信息来生成PFC暂停帧，使得在暂停帧中设置适当的多个使能位。

公开(公告)号：US20160006579A1

公开(公告)日：2016-01-07

申请号：US14321732

申请日：2014-07-01

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb

IPC: H04L12/46 ,  H04L12/741

CPC classification number: H04L12/4625 ,  H04L45/745 ,  H04L49/25

Abstract: A Network Flow Processor (NFP) integrated circuit receives, via each of a first plurality of physical MAC ports, one or more PCP (Priority Code Point) flows. The NFP also maintains, for each of a second plurality of virtual channels, a linked list of buffers. There is one port enqueue engine for each physical MAC port. For each PCP flow received via the physical MAC port associated with a port enqueue engine, the port enqueue engine causes frame data of the flow to be loaded into one particular linked list of buffers. Each port enqueue engine has a lookup table circuit that is configurable to cause multiple PCP flows to be merged so that the frame data for the multiple flows is all assigned to the same one virtual channel. Due to the PCP flow merging, the second number can be smaller than the first number multiplied by eight.

Abstract translation: 网络流处理器（NFP）集成电路经由第一多个物理MAC端口中的每一个接收一个或多个PCP（优先权码点）流。 对于第二多个虚拟通道中的每一个，NFP还维护缓冲器的链接列表。 每个物理MAC端口都有一个端口入队引擎。 对于通过与端口入队引擎相关联的物理MAC端口接收到的每个PCP流，端口入队引擎使流的帧数据被加载到一个特定的缓冲器链表中。 每个端口入队引擎具有可配置为使多个PCP流合并的查找表电路，使得多个流的帧数据都被分配给相同的一个虚拟通道。 由于PCP流合并，第二个数字可以小于第一个数乘以8。

公开(公告)号：US09208844B1

公开(公告)日：2015-12-08

申请号：US14448841

申请日：2014-07-31

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb ,  Chunli Cai ,  Ranjit D. Loboprabhu

IPC: H03K19/00 ,  G11C8/18 ,  G11C8/06

CPC classification number: G11C11/4093 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222

Abstract: An integrated circuit receives a DDR (Double Data Rate) data signal and an associated DDR clock signal, and communicates those signals from integrated circuit input terminals a substantial distance across the integrated circuit to a subcircuit that then receives and uses the DDR data. Within the integrated circuit, a DDR retiming circuit receives the DDR data signal and the associated DDR clock signal from the terminals. The DDR retiming circuit splits the DDR data signal into two components, and then transmits those two components over the substantial distance toward the subcircuit. The subcircuit then recombines the two components back into a single DDR data signal and supplies the DDR data signal and the DDR clock signal to the subcircuit. The DDR data signal and the DDR clock signal are supplied to the subcircuit in such a way that setup and hold time requirements of the subcircuit are met.

Abstract translation: 集成电路接收DDR（双倍数据速率）数据信号和相关联的DDR时钟信号，并将来自集成电路输入端的那些信号跨越集成电路传送到子电路，然后接收并使用DDR数据。 在集成电路中，DDR重定时电路从端子接收DDR数据信号和相关的DDR时钟信号。 DDR重定时电路将DDR数据信号分为两个部分，然后将这两个分量在相当大的距离上发送到子电路。 子电路然后将两个组件重新组合成单​​个DDR数据信号，并将DDR数据信号和DDR时钟信号提供给子电路。 DDR数据信号和DDR时钟信号以满足子电路的建立和保持时间要求的方式提供给子电路。

公开(公告)号：US09264256B2

公开(公告)日：2016-02-16

申请号：US14321732

申请日：2014-07-01

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb

IPC: G06F15/16 ,  H04L12/46 ,  H04L12/741 ,  H04L12/947

CPC classification number: H04L12/4625 ,  H04L45/745 ,  H04L49/25

Abstract: A Network Flow Processor (NFP) integrated circuit receives, via each of a first plurality of physical MAC ports, one or more PCP (Priority Code Point) flows. The NFP also maintains, for each of a second plurality of virtual channels, a linked list of buffers. There is one port enqueue engine for each physical MAC port. For each PCP flow received via the physical MAC port associated with a port enqueue engine, the port enqueue engine causes frame data of the flow to be loaded into one particular linked list of buffers. Each port enqueue engine has a lookup table circuit that is configurable to cause multiple PCP flows to be merged so that the frame data for the multiple flows is all assigned to the same one virtual channel. Due to the PCP flow merging, the second number can be smaller than the first number multiplied by eight.

Abstract translation: 网络流处理器（NFP）集成电路经由第一多个物理MAC端口中的每一个接收一个或多个PCP（优先权码点）流。 对于第二多个虚拟通道中的每一个，NFP还维护缓冲器的链接列表。 每个物理MAC端口都有一个端口入队引擎。 对于通过与端口入队引擎相关联的物理MAC端口接收到的每个PCP流，端口入队引擎使流的帧数据被加载到一个特定的缓冲器链表中。 每个端口入队引擎具有可配置为使多个PCP流合并的查找表电路，使得多个流的帧数据都被分配给相同的一个虚拟通道。 由于PCP流合并，第二个数字可以小于第一个数乘以8。

公开(公告)号：US20160006677A1

公开(公告)日：2016-01-07

申请号：US14321762

申请日：2014-07-01

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb

IPC: H04L12/861 ,  H04L12/931 ,  H04L12/947

CPC classification number: H04L49/3045 ,  H04L49/9005 ,  H04L49/9042 ,  Y02P80/112

Abstract: An overflow threshold value is stored for each of a plurality of virtual channels. A link manager maintains, for each virtual channel, a buffer count. If the buffer count for a virtual channel is detected to exceed the overflow threshold value for a virtual channel whose originating PCP flows were merged, then a PFC (Priority Flow Control) pause frame is generated where multiple ones of the priority class enable bits are set to indicate that multiple PCP flows should be paused. For the particular virtual channel that is overloaded, an Inverse PCP Remap LUT (IPRLUT) circuit performs inverse PCP mapping, including merging and/or reordering mapping, and outputs an indication of each of those PCP flows that is associated with the overloaded virtual channel. Associated physical MAC port circuitry uses this information to generate the PFC pause frame so that the appropriate multiple enable bits are set in the pause frame.

Abstract translation: 为多个虚拟通道中的每一个存储溢出阈值。 链路管理器为每个虚拟通道维护缓冲区计数。 如果检测到虚拟通道的缓冲器计数超过其始发PCP流合并的虚拟通道的溢出阈值，则生成PFC（优先级流控制）暂停帧，其中设置了多个优先级使能位 以指示应暂停多个PCP流。 对于重载的特定虚拟信道，反PCP重映射LUT（IPRLUT）电路执行反PCP映射，包括合并和/或重新排序映射，并且输出与重载虚拟信道相关联的每个PCP流的指示。 相关的物理MAC端口电路使用该信息来生成PFC暂停帧，使得在暂停帧中设置适当的多个使能位。

公开(公告)号：US20160006580A1

公开(公告)日：2016-01-07

申请号：US14321744

申请日：2014-07-01

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb

IPC: H04L12/46 ,  H04L12/947 ,  H04L12/741

CPC classification number: H04L12/467 ,  H04L45/745 ,  H04L49/25

Abstract: A Network Flow Processor (NFP) integrated circuit receives, via each of a plurality of physical MAC ports, PCP (Priority Code Point) flows. The NFP also maintains, for each of a plurality of virtual channels, a linked list of buffers. There is one port enqueue engine for each physical MAC port. For each PCP flow received via the physical MAC port associated with a port enqueue engine, the engine causes frame data of the flow to be loaded into one particular linked list of buffers. Each engine has a lookup table circuit that is configurable so that the relative priorities of the PCP flows are reordered as the PCP flows are assigned to virtual channels. A PCP flow with a higher PCP value can be assigned to a lower priority virtual channel, whereas a PCP flow with a lower PCP value can be assigned to a higher priority virtual channel.

Abstract translation: 网络流处理器（NFP）集成电路通过多个物理MAC端口中的每一个接收PCP（优先代码点）流。 对于多个虚拟通道中的每一个，NFP还维护缓冲器的链接列表。 每个物理MAC端口都有一个端口入队引擎。 对于通过与端口入队引擎相关联的物理MAC端口接收到的每个PCP流，引擎使流的帧数据被加载到一个特定的缓冲器链表中。 每个引擎具有可配置的查找表电路，使得当PCP流被分配给虚拟通道时，PCP流的相对优先级被重新排序。 具有较高PCP值的PCP流可以被分配给较低优先级的虚拟信道，而具有较低PCP值的PCP流可以被分配给较高优先级的虚拟信道。

公开(公告)号：US09891985B1

公开(公告)日：2018-02-13

申请号：US14929275

申请日：2015-10-31

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb ,  Benjamin D. Findlen

IPC: G06F11/10 ,  H03M13/09

CPC classification number: G06F11/1004 ,  H03M13/096

Abstract: A parser and checksum circuit includes a 256-bit data bus, IPV4, IPV6, TCP, and UDP state signal buses, a checksum summer and compare circuit, four 64-bit parsing circuits, a V6 extension processor, and a parse state context circuit. Each of the 64-bit parsing circuits includes two 32-bit parsing circuits. The data bus receives a data signal that is part of a packet. IPV4, IPV6, TCP, and UDP state signals are each configurable into 1-hot states where at most 1-bit is digital logic high. Each of the 1-hot states corresponds to a segment of a packet header of one of the IPV4, IPV6, TCP, and UDP protocols. Each 32-bit parsing circuit receives a 1-bit shifted version of the state signals received by the adjacent 32-bit parsing circuit and receives a portion of the data signal. State signals and the data signal portion are received in parallel during a single clock cycle.

公开(公告)号：US09270488B2

公开(公告)日：2016-02-23

申请号：US14321744

申请日：2014-07-01

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb

IPC: G06F15/16 ,  H04L12/46 ,  H04L12/741 ,  H04L12/947

CPC classification number: H04L12/467 ,  H04L45/745 ,  H04L49/25

Abstract: A Network Flow Processor (NFP) integrated circuit receives, via each of a plurality of physical MAC ports, PCP (Priority Code Point) flows. The NFP also maintains, for each of a plurality of virtual channels, a linked list of buffers. There is one port enqueue engine for each physical MAC port. For each PCP flow received via the physical MAC port associated with a port enqueue engine, the engine causes frame data of the flow to be loaded into one particular linked list of buffers. Each engine has a lookup table circuit that is configurable so that the relative priorities of the PCP flows are reordered as the PCP flows are assigned to virtual channels. A PCP flow with a higher PCP value can be assigned to a lower priority virtual channel, whereas a PCP flow with a lower PCP value can be assigned to a higher priority virtual channel.

Abstract translation: 网络流处理器（NFP）集成电路通过多个物理MAC端口中的每一个接收PCP（优先代码点）流。 对于多个虚拟通道中的每一个，NFP还维护缓冲器的链接列表。 每个物理MAC端口都有一个端口入队引擎。 对于通过与端口入队引擎相关联的物理MAC端口接收到的每个PCP流，引擎使流的帧数据被加载到一个特定的缓冲器链表中。 每个引擎具有可配置的查找表电路，使得当PCP流被分配给虚拟通道时，PCP流的相对优先级被重新排序。 具有较高PCP值的PCP流可以被分配给较低优先级的虚拟信道，而具有较低PCP值的PCP流可以被分配给较高优先级的虚拟信道。

公开(公告)号：US20160006665A1

公开(公告)日：2016-01-07

申请号：US14321756

申请日：2014-07-01

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb

IPC: H04L12/863

CPC classification number: H04L47/622

Abstract: Incoming frame data is stored in a plurality of dual linked lists of buffers in a pipelined memory. The dual linked lists of buffers are maintained by a link manager. The link manager maintains, for each dual linked list of buffers, a first head pointer, a second head pointer, a first tail pointer, a second tail pointer, a head pointer active bit, and a tail pointer active bit. The first head and tail pointers are used to maintain the first linked list of the dual linked list. The second head and tail pointers are used to maintain the second linked list of the dual linked list. Due to the pipelined nature of the memory, the dual linked list system can be popped to supply dequeued values at a sustained rate of more than one value per the read access latency time of the pipelined memory.

Abstract translation: 输入帧数据被存储在流水线存储器中的多个缓冲器的双链表中。 缓冲区的双链表由链接管理器维护。 链路管理器针对缓冲器的每个双链表维护第一头指针，第二头指针，第一尾指针，第二尾指针，头指针活动位和尾指针有效位。 第一个头和尾指针用于维护双链表的第一个链表。 第二个头尾指针用于维护双链表的第二个链表。 由于存储器的流水线性质，可以弹出双链表系统以便以流水线存储器的读取访问等待时间为单位以多于一个值的持续速率提供出队值。