公开(公告)号：US20250093931A1

公开(公告)日：2025-03-20

申请号：US18468242

申请日：2023-09-15

Applicant: QUALCOMM Incorporated

Inventor： Mahadevamurty Nemani ,  Anubhav Mishra ,  Arun Sukheja ,  Nitin Makhija ,  Adarsh Baraka Ravi

IPC: G06F1/28 ,  G06F9/445

Abstract: Autonomously managing core cluster frequencies using performance statistics in processor devices is disclosed herein. In some aspects, a cluster power management circuit of a processor device collects Activity Management Unit (AMU) statistics for multiple processor cores for each of one or more frequency operating points over a time interval. Based on the AMU statistics, the cluster power management circuit generates a performance model representing processor performance as a function of frequency, and uses the performance model and a power consumption measurement to generate an energy-per-instruction (EI) model representing energy per instruction as a function of frequency. The cluster power management circuit then generates an advantage model based on a first rate of change of the performance model as a function of frequency and a second rate of change of the EI model as a function of frequency, and identifies a target frequency operating point based on the advantage model.

公开(公告)号：US20250094182A1

公开(公告)日：2025-03-20

申请号：US18469630

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Mahadevamurty Nemani ,  Sneha Wani ,  Mohd Imran Beg ,  Nitin Makhija ,  Arun Sukheja

IPC: G06F9/448

Abstract: Performing dynamic microarchitectural throttling of processor cores based on Quality-of-Service (QOS) levels in processor devices is disclosed herein. In some aspects, a processor device comprises a synchronous core cluster including a plurality of processor cores, a throttling selection circuit, and a throttling circuit. The throttling selection circuit receives a QoS level associated with a workload scheduled for execution by a processor core. The throttling selection circuit determines a performance state of the processor core, and determines a throttling level for the processor core, based on the QoS level and the performance state. The throttling selection circuit provides the throttling level to the throttling circuit, which performs microarchitectural throttling of the processor core based on the throttling level.

公开(公告)号：US20250103130A1

公开(公告)日：2025-03-27

申请号：US18475371

申请日：2023-09-27

Applicant: QUALCOMM Incorporated

Inventor： Mahadevamurty Nemani ,  Matthew Severson ,  Gabriel Watkins ,  Vijayakumar Ashok Dibbad ,  Ronald Alton ,  Lai Xu ,  Jeffrey Gemar

IPC: G06F1/3296 ,  G06F1/3206

Abstract: Power limiting in a processor-based system based on allocating power budgets for different sub-systems based on multiple time-based power limits is disclosed. The processor-based system has multiple power consuming sub-systems (e.g., non-processing unit (PU) and PU sub-systems) that demand and consume power from a power source of the processor-based system. To limit overall power consumption of the processor-based system over different time-based power limits, the processor-based system includes a power limiter circuit. The power limiter circuit is configured to manage multiple, different time-based (e.g., time constant) power limits for the processor-based system and to allocate corresponding power limit budgets to constrain power consumption of different sub-systems based on the multiple time-based power limits. The power limiter circuit can be configured to constrain power consumption of a PU sub-system to a total PU sub-system power limit budget based on the multiple time-based power limits.

公开(公告)号：US20250093942A1

公开(公告)日：2025-03-20

申请号：US18469890

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Mahadevamurty Nemani ,  Adarsh Baraka Ravi ,  Nitin Makhija ,  Pradeep Kanapathipillai

IPC: G06F1/3296 ,  G06F1/3206

Abstract: Power sources provide power in a range with a maximum supply voltage provided under zero-load current conditions. Power circuits in an IC receive and aggregate indications of load current from processor circuits in processor circuit clusters and, reduce power consumption in the IC during zero or low load current conditions by generating a voltage control signal to reduce the supply voltage. Reducing the no-load voltage also reduces stress on gate oxides of transistors in the IC to increase oxide longevity. Based on the aggregated load current indications, which is periodically updated, the no-load supply voltage may be incrementally reduced down to a voltage threshold over the course of multiple periods. In some examples, the power circuits receive throttle signals when the processor circuits are throttled due to a voltage droop, and such signals may cause the power circuits to generate a control signal to increase the no-load voltage.

公开(公告)号：US11783042B2

公开(公告)日：2023-10-10

申请号：US16903982

申请日：2020-06-17

Applicant: QUALCOMM INCORPORATED

Inventor： Steven Halter ,  Samar Asbe ,  Miguel Ballesteros ,  Girish Bhat ,  Mahadevamurty Nemani

IPC: G06F21/57 ,  G06F9/445 ,  G06F9/50 ,  G06F21/62

CPC classification number: G06F21/575 ,  G06F9/445 ,  G06F9/5016 ,  G06F21/572 ,  G06F21/62 ,  G06F2221/034

Abstract: Resource access control in a system-on-chip (“SoC”) may employ an agent executing on a processor of the SoC and a trust management engine of the SoC. The agent, such as, for example, a high-level operating system or a hypervisor, may be configured to allocate a resource comprising a memory region to an access domain and to load a software image associated with the access domain into the memory region. The trust management engine may be configured to lock the resource against access by any entity other than the access domain, to authenticate the software image associated with the access domain, and to initiate booting of the access domain in response to a successful authentication of the software image associated with the access domain.

公开(公告)号：US09519041B2

公开(公告)日：2016-12-13

申请号：US14465767

申请日：2014-08-21

Applicant: Qualcomm Incorporated

Inventor： Mahadevamurty Nemani

IPC: G01R35/00 ,  G01K13/00 ,  G06F1/26

CPC classification number: G01R35/005 ,  G01K13/00 ,  G06F1/08 ,  G06F1/26

Abstract: Systems and methods for calibrating on-die analog current sensors are disclosed. The methods can be routinely applied to perform a calibration such as during a system initialization or boot procedure or during other times when the system is in a sleep or power saving mode of operation. The systems determine a leakage current in the device under present environmental conditions. A baseline load current determined under the present temperature and input voltage is retrieved and used to determine a total leakage current. A reproducible and stable dynamic load is controllably applied to provide a known current to the on-die analog current sensor. A third mechanism permits repeatable adjustments to the known current that span the operational range of the on-die integrated current sensor. The responsiveness of the disclosed mechanisms ensures that temperature induced leakage does not increase significantly during a current sensor calibration.

Abstract translation: 公开了用于校准模内模拟电流传感器的系统和方法。 可以常规地应用这些方法来执行校准，例如在系统初始化或引导过程期间或在系统处于睡眠或省电操作模式的其他时间期间。 系统确定了目前环境条件下器件中的漏电流。 检索在当前温度和输入电压下确定的基准负载电流，并用于确定总泄漏电流。 可控制地施加可再现和稳定的动态负载以向芯片上模拟电流传感器提供已知电流。 第三种机构允许可重复地调整跨越集成式电流传感器的工作范围的已知电流。 所公开的机构的响应性确保了在当前传感器校准期间温度感应泄漏不会显着增加。