公开(公告)号：US20140374873A1

公开(公告)日：2014-12-25

申请号：US14484904

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Sundararajan Ranganathan ,  Paras Gupta ,  Raghavendra Dasegowda ,  Rajesh Verma ,  Parissa Najdesamii

IPC: H01L23/538 ,  G06F17/50

CPC classification number: H01L23/538 ,  G06F17/5077 ,  G06F2217/78 ,  H01L27/0203 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Abstract translation: 本文提供了一种半导体装置，用于缓冲通过与第一功率域相关联的一个或多个区域路由的网络，所述第一功率域不同于与缓冲器和缓冲网络相关联的第二功率域，通过将这些缓冲器的位置限制在与 第二功率域。 这提供了缓冲网络的路由，其不仅将基于从点A到点B行进的最短距离而被确定，而且还考虑了半导体装置上的路由拥塞。 因此，如果半导体装置上的区域拥塞，则缓冲网可以围绕拥塞进行路由。 因此，尽管通过集成电路的特定信号所采取的路径不是直接路由，但是它仍然可以是支持特定信号需要传送的速度的距离。

公开(公告)号：US10396033B1

公开(公告)日：2019-08-27

申请号：US16042937

申请日：2018-07-23

Applicant: QUALCOMM Incorporated

Inventor： Paras Gupta ,  Aklesh Jain ,  Kelageri Nagaraj ,  V Karthik Venkataraman

IPC: H01L23/528 ,  H03K17/687

Abstract: Methods and apparatuses for efficiently providing supply voltages to a load circuit are provided. The apparatus includes a first plurality of first power buses extending in a first direction and within a first range. The first range extends in a second direction. A second plurality of first power buses extends in the first direction and within the first range. The first plurality of first power buses and the second plurality of first power buses are powered at a first supply voltage. A plurality of second power buses extends in the first direction within the first range and a second range. The second range extends in the first direction. The plurality of second power buses is powered at a second supply voltage. The first plurality of first power buses, the second plurality of first power buses, and the plurality of second power buses are in a conductive layer.

公开(公告)号：US11047946B2

公开(公告)日：2021-06-29

申请号：US15974271

申请日：2018-05-08

Applicant: QUALCOMM Incorporated

Inventor： Nam Dang ,  Rajeev Jain ,  Swarna Navubothu ,  Alan Lewis ,  Martin Saint-Laurent ,  Tung Nang Pham ,  Joseph Terregrossa ,  Paras Gupta ,  Somasekhar Maradani

IPC: G01R35/00 ,  G01R19/25 ,  H03K5/003

Abstract: Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.

公开(公告)号：US09190358B2

公开(公告)日：2015-11-17

申请号：US14484904

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Sundararajan Ranganathan ,  Paras Gupta ,  Raghavendra Dasegowda ,  Rajesh Verma ,  Parissa Najdesamii

IPC: H01L29/00 ,  H01L21/82 ,  H01L23/538 ,  G06F17/50 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L23/538 ,  G06F17/5077 ,  G06F2217/78 ,  H01L27/0203 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Abstract translation: 本文提供了一种半导体装置，用于缓冲通过与第一功率域相关联的一个或多个区域路由的网络，所述第一功率域不同于与缓冲器和缓冲网络相关联的第二功率域，通过将这些缓冲器的位置限制在与 第二功率域。 这提供了缓冲网络的路由，其不仅将基于从点A到点B行进的最短距离而被确定，而且还考虑了半导体装置上的路由拥塞。 因此，如果半导体装置上的区域拥塞，则缓冲网可以围绕拥塞进行路由。 因此，尽管通过集成电路的特定信号所采取的路径不是直接路由，但是它仍然可以是支持特定信号需要传送的速度的距离。

公开(公告)号：US08853815B1

公开(公告)日：2014-10-07

申请号：US13831360

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Sundararajan Ranganathan ,  Paras Gupta ,  Raghavendra Dasegowda ,  Rajesh Verma ,  Parissa Najdesamii

IPC: H01L29/00 ,  H01L21/82 ,  G06F17/50 ,  H01L29/06

CPC classification number: H01L23/538 ,  G06F17/5077 ,  G06F2217/78 ,  H01L27/0203 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Abstract translation: 本文提供了一种半导体装置，用于缓冲通过与第一功率域相关联的一个或多个区域路由的网络，所述第一功率域不同于与缓冲器和缓冲网络相关联的第二功率域，通过将这些缓冲器的位置限制在与 第二功率域。 这提供了缓冲网络的路由，其不仅将基于从点A到点B行进的最短距离而被确定，而且还考虑了半导体装置上的路由拥塞。 因此，如果半导体装置上的区域拥塞，则缓冲网可以围绕拥塞进行路由。 因此，尽管通过集成电路的特定信号所采取的路径不是直接路由，但是它仍然可以是支持特定信号需要传送的速度的距离。

公开(公告)号：US20180342460A1

公开(公告)日：2018-11-29

申请号：US15605843

申请日：2017-05-25

Applicant: QUALCOMM Incorporated

Inventor： Sreedhar Gudala ,  Paras Gupta ,  Ranganayakulu Konduri

IPC: H01L23/528 ,  H01L23/48 ,  G06F17/50

Abstract: In certain aspects of the disclosure, a chip includes a power distribution network for distributing power to device on the chip. The power distribution network includes a first portion formed from a first metal layer on the chip, a second portion formed from a second metal layer on the chip, and vias interconnecting the first and second portions of the power distribution network, wherein the vias include a first plurality of vias and a second plurality of vias, each one of the first plurality of vias has a first via size, and each one of the second plurality of vias has a second via size. The devices on the chip are electrically coupled to the first portion of the power distribution network.

公开(公告)号：US09483600B2

公开(公告)日：2016-11-01

申请号：US14645336

申请日：2015-03-11

Applicant: QUALCOMM Incorporated

Inventor： Mamta Bansal ,  Uday Doddannagari ,  Paras Gupta ,  Ramaprasath Vilangudipitchai ,  Parissa Najdesamii ,  Dorav Kumar ,  Nitin Partani

IPC: H01L25/00 ,  G06F17/50 ,  H01L27/02 ,  H04W72/04 ,  H01L23/528 ,  H01L27/092

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H04W72/0453 ,  Y02D70/00 ,  H01L2924/00

Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Abstract translation: MOS器件包括多个标准单元，其被配置为减少路由拥塞，同时在MOS器件上提供区域节省。 标准细胞可以是共享与其他附近n型孔分离的n型井的单高度标准细胞。 单个高度标准单元的输入和输出信号引脚可以配置在最低可能的金属层（例如，M1）中，而单高度标准单元的次级电源引脚可以配置在较高的金属层（例如，M2 ）。 为次级电源引脚供电的互连可以沿着垂直轨道配置，并在不同的标准单元组之间共享，这可以减少在MOS器件中使用的垂直轨道的数量。 MOS器件中可用的水平路由轨迹的数量可能不受影响，因为主电源/接地网格已经使用的水平轨迹用于电源连接。

公开(公告)号：US20140264715A1

公开(公告)日：2014-09-18

申请号：US13831360

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Sundararajan Ranganathan ,  Paras Gupta ,  Raghavendra Dasegowda ,  Rajesh Verma ,  Parissa Najdesamii

IPC: G06F17/50 ,  H01L29/06

CPC classification number: H01L23/538 ,  G06F17/5077 ,  G06F2217/78 ,  H01L27/0203 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.