公开(公告)号：US20220093594A1

公开(公告)日：2022-03-24

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Deepak SHARMA ,  Bharani CHAVA ,  Hyeokjin LIM ,  Peijie FENG ,  Seung Hyuk KANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  Kern RIM ,  Giridhar NALLAPATI ,  Venugopal BOYNAPALLI ,  Foua VANG

IPC: H01L27/095 ,  H03K19/0185 ,  H01L23/528 ,  H01L29/78

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US20250098267A1

公开(公告)日：2025-03-20

申请号：US18469473

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Yan SUN ,  Deepak SHARMA ,  Shreesh NARASIMHA

IPC: H01L29/417 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a gate stack including a first gate structure and a second gate structure offset in a first direction. The semiconductor structure includes a first source/drain (S/D) structure adjacent the first gate structure, a second S/D structure adjacent the second gate structure, a first backside conductive structure in contact with the first S/D structure, and a second backside conductive structure in contact with the second S/D structure. The semiconductor structure includes a third backside conductive structure disposed in a back portion of the semiconductor structure opposing a front portion of the semiconductor structure, extending along a second direction, and in contact with the first backside conductive structure and the second backside conductive structure.

公开(公告)号：US20250098301A1

公开(公告)日：2025-03-20

申请号：US18469483

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Deepak SHARMA ,  Yan SUN ,  Shreesh NARASIMHA

IPC: H01L27/12 ,  H01L21/768 ,  H01L23/528 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed are gate-tie-down (GTD) cells that utilize a backside power delivery scheme, where metal wires that deliver power are provided on the back of the wafer. As a result, ultra-low height standard cell can be enabled. Also higher area scaling may be achieved. Further, performance and power gain can be maximized.

公开(公告)号：US20250098204A1

公开(公告)日：2025-03-20

申请号：US18469489

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Deepak SHARMA ,  Yan SUN ,  Shreesh NARASIMHA

IPC: H01L29/78 ,  H01L27/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66

Abstract: Disclosed are gate-tie-down (GTD) cells that utilize a backside power delivery scheme, where metal wires that deliver power are provided on the back of the die. The backside power may be delivered to the gates through S/Ds and through frontside contacts. As a result, ultra-low height standard cell can be enabled. Also higher area scaling may be achieved. Further, performance and power gain can be maximized.

公开(公告)号：US20240105728A1

公开(公告)日：2024-03-28

申请号：US18472074

申请日：2023-09-21

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Haining YANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  George Pete IMTHURN ,  Jun YUAN ,  Giridhar NALLAPATI ,  Deepak SHARMA

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11853 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: Disclosed are standard cells, transistors, and methods for fabricating the same. In an aspect, a transistor includes a drain and a source each including a first drain/source silicide layer on a frontside surface of the drain/source and a second drain/source silicide layer on a backside surface of the drain/source. The first drain silicide layer is coupled to a first drain contact structure or the second drain silicide layer is coupled to a second drain contact structure. The first source silicide layer is coupled to a first source contact structure or the second source silicide layer is coupled to a second source contact structure. A gate structure is disposed between the source and the drain. A channel is at least partially enclosed by the gate structure and disposed between the source and the drain and is recessed from the backside surfaces of the source and drain.

公开(公告)号：US20250098217A1

公开(公告)日：2025-03-20

申请号：US18469496

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Yan SUN ,  Shreesh NARASIMHA ,  Deepak SHARMA

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a FET structure comprises a gate structure, disposed between a first vertical source/drain (S/D) structure and a second vertical S/D structure, the gate structure comprising a channel structure comprising a plurality of vertically-stacked, horizontal channels connecting the first vertical S/D structure to the second vertical S/D structure horizontally through a vertical metal gate structure that at least partially surrounds the plurality of horizontal channels. The FET also comprises a backside inter-layer dielectric (ILD) layer disposed below the vertical metal gate structure, wherein a first thickness of the vertical metal gate structure below a bottom channel of the plurality of horizontal channels is larger than a second thickness of the vertical metal gate structure between adjacent channels of the plurality of horizontal channels.

公开(公告)号：US20250098302A1

公开(公告)日：2025-03-20

申请号：US18469505

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN ,  Deepak SHARMA

IPC: H01L27/12

Abstract: Compact logic cells using full backside connectivity are disclosed. In an aspect, a semiconductor device comprises a plurality of integrated circuit cells comprising: gates separated by source/drain (S/D) structures and comprising at least one channel extending through a metal structure and connecting adjacent S/D structures to each other, at least one gate forming a gate-all-around field effect transistor; an FS contact electrically connecting to an S/D structure; an FS contact electrically connecting to a gate; a frontside (FS) inter-layer dielectric (ILD) on the gates and S/D structures; FS metal zero interconnects disposed on the FS-ILD, one being electrically connected to an FS contact; a BS contact electrically connecting to an S/D structure; a BS contact electrically connecting to a gate; a backside (BS) ILD disposed on the gates and S/D structures; and BS metal zero interconnects disposed on the BS-ILD, one being electrically connected to a BS contact.

公开(公告)号：US20250096130A1

公开(公告)日：2025-03-20

申请号：US18824706

申请日：2024-09-04

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN ,  Deepak SHARMA

IPC: H01L23/528 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a FET structure comprises a gate structure, disposed between a first vertical source/drain (S/D) structure and a second vertical S/D structure, the gate structure comprising a channel structure comprising a plurality of vertically-stacked, horizontal channels connecting the first vertical S/D structure to the second vertical S/D structure in a first horizontal direction through a vertical metal gate structure that at least partially surrounds the plurality of vertically-stacked, horizontal channels. The FET also comprises a backside inter-layer dielectric (ILD) layer disposed below the vertical metal gate structure, wherein a first thickness of the vertical metal gate structure below a bottom channel of the plurality of vertically-stacked, horizontal channels is larger than a second thickness of the vertical metal gate structure between adjacent channels of the plurality of vertically-stacked, horizontal channels.