公开(公告)号：US20220093594A1

公开(公告)日：2022-03-24

申请号：US17025211

申请日：2020-09-18

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul SONG ,  Deepak SHARMA ,  Bharani CHAVA ,  Hyeokjin LIM ,  Peijie FENG ,  Seung Hyuk KANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  Kern RIM ,  Giridhar NALLAPATI ,  Venugopal BOYNAPALLI ,  Foua VANG

IPC分类号： H01L27/095 ,  H03K19/0185 ,  H01L23/528 ,  H01L29/78

摘要： Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US20240266342A1

公开(公告)日：2024-08-08

申请号：US18165259

申请日：2023-02-06

申请人： QUALCOMM Incorporated

发明人： Renukprasad HIREMATH ,  Hyeokjin LIM ,  Foua VANG ,  Manjanaika CHANDRANAIKA ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC分类号： H01L27/02 ,  G06F30/392

CPC分类号： H01L27/0207 ,  G06F30/392

摘要： A chip includes a first column including first rails extending in a first direction, the first rails having a first pitch. The chip also includes a second column including second rails extending in the first direction, the second rails having a second pitch different from the first pitch. The chip also includes a transition region between the first column and the second column.

公开(公告)号：US20180122824A1

公开(公告)日：2018-05-03

申请号：US15855996

申请日：2017-12-27

申请人： QUALCOMM Incorporated

发明人： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON ,  Foua VANG ,  Stanley Seungchul SONG ,  Kern RIM

IPC分类号： H01L27/118 ,  H01L27/02 ,  H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

摘要： A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.

公开(公告)号：US20220094363A1

公开(公告)日：2022-03-24

申请号：US17030087

申请日：2020-09-23

申请人： QUALCOMM Incorporated

发明人： Foua VANG ,  Hyeokjin LIM ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI ,  Shitiz ARORA

IPC分类号： H03K19/094 ,  H01L23/528

摘要： A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mx layer interconnects on an Mx layer extending in a first direction over the first and second subcells. A first subset of the first set of Mx layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mx layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.

公开(公告)号：US20150302129A1

公开(公告)日：2015-10-22

申请号：US14255677

申请日：2014-04-17

申请人： QUALCOMM Incorporated

发明人： Xiangdong CHEN ,  Mukul GUPTA ,  Ohsang KWON ,  Foua VANG

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G03F1/70 ,  G03F7/70466

摘要： In an embodiment, a method in the manufacture of triple-patterning lithography masks, each mask represented by one of three colors, where each cell layout has exactly one polygonal pattern at one-half the different-color spacing from its left boundary, and exactly one polygonal pattern at one-half the different-color spacing from its right boundary. During placement of the cell layouts into a row, the method includes switching assigned colors in a cell layout to ensure that no two polygonal patterns of the same color in the layout are at a distance from each other less than the same-color spacing.

摘要翻译： 在一个实施例中，制造三重图案化光刻掩模的方法，每个掩模由三种颜色之一表示，其中每个单元布局具有与其左边界不同的颜色间隔的一半的正好一个多边形图案，并且精确地 一个多边形图案与其右边界的不同颜色间距的一半。 在将单元格布局放置到行中的过程中，该方法包括切换单元格布局中分配的颜色，以确保布局中相同颜色的两个多边形图案彼此之间的距离小于相同颜色的间距。

公开(公告)号：US20210280571A1

公开(公告)日：2021-09-09

申请号：US16808336

申请日：2020-03-03

申请人： QUALCOMM Incorporated

发明人： Hyeokjin LIM ,  Bharani CHAVA ,  Foua VANG ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC分类号： H01L27/02 ,  H01L23/528 ,  H03K19/0185

摘要： A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2≤m m*P

公开(公告)号：US20160370699A1

公开(公告)日：2016-12-22

申请号：US15182510

申请日：2016-06-14

申请人： QUALCOMM Incorporated

发明人： Xiangdong CHEN ,  Hyeokjin Bruce LIM ,  Ohsang KWON ,  Mickael MALABRY ,  Jingwei ZHANG ,  Raymond George STEPHANY ,  Haining YANG ,  Kern RIM ,  Stanley Seungchul SONG ,  Mukul GUPTA ,  Foua VANG

IPC分类号： G03F1/70 ,  G06F17/50

CPC分类号： G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5068

摘要： In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

摘要翻译： 在本公开的一个方面，提供了一种方法，计算机可读介质和用于分配多个图案化处理的特征颜色的装置。 该装置接收集成电路布局信息，该信息包括一组特征的集合，以及针对特征集合的第一特征集的每个特征的多种颜色的分配颜色。 另外，该装置对特征的第二子集执行颜色分解，以将颜色分配给第二特征子集中的特征。 特征的第二子集包括不包括在具有分配颜色的特征的第一子集中的特征集合中的特征。

公开(公告)号：US20150333008A1

公开(公告)日：2015-11-19

申请号：US14279250

申请日：2014-05-15

申请人： QUALCOMM Incorporated

发明人： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON ,  Foua VANG ,  Stanley Seungchul SONG ,  Kern RIM

IPC分类号： H01L23/535 ,  H01L27/02 ,  H01L27/092

CPC分类号： H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

摘要： A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.

摘要翻译： 标准单元CMOS器件包括具有由栅极互连形成的栅极的金属氧化物半导体晶体管。 栅极互连沿第一方向延伸。 该器件还包括向晶体管提供功率的电源轨。 电源轨在与第一方向正交的第二方向上延伸。 该装置还包括在电源轨之间延伸的M1层互连。 M1层互连中的至少一个耦合到至少一个晶体管。 M1层互连平行于栅极互连并仅在第一方向上延伸。

公开(公告)号：US20240249056A1

公开(公告)日：2024-07-25

申请号：US18156999

申请日：2023-01-19

申请人： QUALCOMM Incorporated

发明人： Hyeokjin LIM ,  Ankur MEHROTRA ,  Renukprasad HIREMATH ,  Foua VANG ,  Manjanaika CHANDRANAIKA ,  Akhtar ALAM ,  Kamesh MEDISETTI ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC分类号： G06F30/392 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/528 ,  H01L27/02

CPC分类号： G06F30/392 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5286 ,  H01L27/0207

摘要： A chip includes a spare cell including a first active region, and a first gate extending over the first active region in a first direction. The chip also includes a tie cell including a second active region, a second gate extending over the second active region in the first direction, a first drain contact formed over the second active region, a first source contact formed over the second active region, wherein the second gate is between the first drain contact and the first source contact, and first source contact is coupled to a first rail, and a circuit configured to couple the second gate to a second rail. The chip also includes a metal routing extending in a second direction, wherein the second direction is perpendicular to the first direction, and the first metal routing is coupled to the first drain contact and the first gate.

公开(公告)号：US20220115405A1

公开(公告)日：2022-04-14

申请号：US17065746

申请日：2020-10-08

申请人： QUALCOMM Incorporated

发明人： Hyeokjin LIM ,  Venugopal BOYNAPALLI ,  Foua VANG ,  Seung Hyuk KANG

IPC分类号： H01L27/118

摘要： A MOS IC includes first and second sets of adjacent transistor logic, each of which include collinear gate interconnects extending in a first direction with the same gate pitch. The first set of transistor logic has a first cell height h1 and a first number of Mx layer tracks that extend unidirectionally in a second direction orthogonal to the first direction. The second set of transistor logic has a second cell height h2 and a second number of Mx layer tracks that extend unidirectionally in the second direction, where h2>h1 and the second number of Mx layer tracks is greater than the first number of Mx layer tracks. At least one of a height ratio hR=h2/h1 is a non-integer value or a subset of the first set of transistor logic and a subset of the second set of transistor logic are within one logic cell.