公开(公告)号：US20230307817A1

公开(公告)日：2023-09-28

申请号：US17651324

申请日：2022-02-16

Applicant: QUALCOMM Incorporated

Inventor： Suhyung Hwang ,  Kun Fang ,  Jaehyun Yeon ,  Chin-Kwan Kim ,  Taesik Yang

IPC: H01Q1/22 ,  H01Q9/04 ,  H01Q21/06

CPC classification number: H01Q1/2283 ,  H01Q9/045 ,  H01Q21/065

Abstract: Antenna modules employing a package substrate with a vertically-integrated patch antenna(s), and related fabrication methods. The antenna module includes a radiofrequency (RF) IC (RFIC) package that includes one or more RFICs for supporting RF communications and a package substrate that includes one or more metallization layers with formed metal interconnects for routing of signals between the RFICs and an antenna(s) in the package substrate. The package substrate includes one or more patch antennas that are planar-shaped and vertically integrated in a plurality of metallization layers in the package substrate, behaving electromagnetically as a patch antenna. In this manner, the patch antenna(s) can be formed as a vertically-integrated structure in the package substrate with fabrication methods used for fabricating metal interconnects and vias (e.g., a micro via fabrication process) in package substrates.

公开(公告)号：US12293980B2

公开(公告)日：2025-05-06

申请号：US16870642

申请日：2020-05-08

Applicant: QUALCOMM Incorporated

Inventor： Jaehyun Yeon ,  Suhyung Hwang ,  Chin-Kwan Kim ,  Rajneesh Kumar ,  Darryl Sheldon Jessie

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01Q1/22 ,  H01Q1/52 ,  H01Q5/307 ,  H01Q9/16 ,  H01Q21/06

Abstract: A package comprising a substrate, a first antenna device, and an integrated device. The substrate comprising a first surface and a second surface, where the substrate comprises a plurality of interconnects. The first antenna device is coupled to the first surface of the substrate, through a first plurality of solder interconnects. The integrated device is coupled to the second surface of the substrate. The package may include an encapsulation layer located over the second surface of the substrate, where the encapsulation layer encapsulates the integrated device. The package may include a shield formed over a surface of the encapsulation layer, where the shield includes an electromagnetic interference (EMI) shield.

公开(公告)号：US11183446B1

公开(公告)日：2021-11-23

申请号：US16994910

申请日：2020-08-17

Applicant: QUALCOMM Incorporated

Inventor： Jaehyun Yeon ,  Suhyung Hwang ,  Hong Bok We ,  Kun Fang

IPC: H05K1/02 ,  H01L23/498 ,  H05K1/11 ,  H05K3/40 ,  H05K3/10

Abstract: X.5 layer substrates that do not use an embedded traces substrate process during formation may produce a high yield with relaxed L/S in a short manufacturing time (only 4× lamination process without a detach process) at a low cost. For example, a substrate may include an mSAP, two landing pads, two escape lines, two bump pads, and a photo-imageable dielectric layer on the mSAP patterned substrate.

公开(公告)号：US11101220B2

公开(公告)日：2021-08-24

申请号：US16553283

申请日：2019-08-28

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Aniket Patil ,  Jaehyun Yeon

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/498 ,  H01L21/50 ,  H01L21/768 ,  H01L21/60

Abstract: Certain aspects of the present disclosure generally relate to a chip package having through-package partial vias. An example chip package generally includes a first substrate, a second substrate, an integrated circuit die, and one or more conductive vias. The integrated circuit die is disposed between the first substrate and the second substrate. The one or more conductive vias are disposed on at least one edge of at least one of the first substrate or the second substrate and electrically coupled to at least one of the first substrate or the second substrate.

公开(公告)号：US20230282959A1

公开(公告)日：2023-09-07

申请号：US17653061

申请日：2022-03-01

Applicant: QUALCOMM Incorporated

Inventor： Jaehyun Yeon ,  Kun Fang ,  Suhyung Hwang ,  Hyunchul Cho

IPC: H01Q1/22 ,  H01Q1/42

CPC classification number: H01Q1/2283 ,  H01Q1/2208 ,  H01Q1/422

Abstract: Multi-directional antenna modules employing a surface-mount antenna(s) to support antenna pattern mufti-directionality, and related fabrication methods. The antenna module includes a radio-frequency (RF) IC (RFIC) package that includes one or more RFICs for supporting RF communications and a package substrate that includes one or more metallization layers with formed metal interconnects for routing of signals between the RFICs and multiple antennas in the package substrate. To provide multi-directionality in antenna radiation patterns, a first antenna is provided that is coupled to the package substrate and oriented in a first plane, and a second antenna is provided that coupled to the package substrate and oriented in a second plane orthogonal to the first plane. In an example, the second antenna is packaged in an antenna package that includes external metal pads that when surface mounted to the package substrate, cause the second antenna to oriented in the second plane.

公开(公告)号：US11545425B2

公开(公告)日：2023-01-03

申请号：US17066318

申请日：2020-10-08

Applicant: QUALCOMM Incorporated

Inventor： Kun Fang ,  Jaehyun Yeon ,  Suhyung Hwang ,  Hong Bok We

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A substrate that includes a core layer, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, a plurality of first interconnects located over a surface of the at least one first dielectric layer, a plurality of second interconnects located over the surface of the at least one first dielectric layer, a plurality of third interconnects located over the surface of the at least one first dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. The plurality of third interconnects and the plurality of second interconnects are co-planar to the plurality of first interconnects. The solder resist layer includes a first portion, a second portion, and a third portion.

公开(公告)号：US11439008B2

公开(公告)日：2022-09-06

申请号：US17149498

申请日：2021-01-14

Applicant: QUALCOMM Incorporated

Inventor： Kun Fang ,  Jaehyun Yeon ,  Suhyung Hwang ,  Hyunchul Cho ,  Boyu Tseng

IPC: H05K1/11 ,  H01L21/48 ,  H05K1/02

Abstract: A package that includes a substrate and an electrical component coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, and a solder resist layer located over a surface of the at least one dielectric layer. The solder resist layer includes a first solder resist layer portion comprising a first thickness, and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The electrical component is located over the second solder resist layer portion.

公开(公告)号：US11075260B2

公开(公告)日：2021-07-27

申请号：US16176915

申请日：2018-10-31

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Chin-Kwan Kim ,  Hong Bok We ,  Jaehyun Yeon

IPC: H01L23/498 ,  H01L49/02 ,  H01L21/56 ,  H01L23/31

Abstract: A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect.

公开(公告)号：US11043740B2

公开(公告)日：2021-06-22

申请号：US16411883

申请日：2019-05-14

Applicant: QUALCOMM Incorporated

Inventor： Suhyung Hwang ,  Chin-Kwan Kim ,  Hong Bok We ,  Jaehyun Yeon

IPC: H01Q1/52

Abstract: Methods and apparatuses for enhancing antenna modules with a shield layer. The apparatus includes an antenna module having an antenna layer. The antenna layer includes an antenna. The antenna module further includes a signal routing layer; a radio frequency (RF) communication component disposed on the signal routing layer; a shield cover encasing the RF communication component; and a shield layer. The antenna module further includes an antenna module side. The antenna module side includes a side of the signal routing layer and a side of the antenna layer. The shield layer covers a portion of the antenna module side such that at least a portion of the side of the antenna layer is uncovered.

公开(公告)号：US12300873B2

公开(公告)日：2025-05-13

申请号：US17651324

申请日：2022-02-16

Applicant: QUALCOMM Incorporated

Inventor： Suhyung Hwang ,  Kun Fang ,  Jaehyun Yeon ,  Chin-Kwan Kim ,  Taesik Yang

IPC: H01Q1/22 ,  H01Q9/04 ,  H01Q21/06

Abstract: Antenna modules employing a package substrate with a vertically-integrated patch antenna(s), and related fabrication methods. The antenna module includes a radio-frequency (RF) IC (RFIC) package that includes one or more RFICs for supporting RF communications and a package substrate that includes one or more metallization layers with formed metal interconnects for routing of signals between the RFICs and an antenna(s) in the package substrate. The package substrate includes one or more patch antennas that are planar-shaped and vertically integrated in a plurality of metallization layers in the package substrate, behaving electromagnetically as a patch antenna. In this manner, the patch antenna(s) can be formed as a vertically-integrated structure in the package substrate with fabrication methods used for fabricating metal interconnects and vias (e.g., a micro via fabrication process) in package substrates.