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    BIAS GENERATION AND DISTRIBUTION FOR A LARGE ARRAY OF SENSORS
    2.
    发明申请
    BIAS GENERATION AND DISTRIBUTION FOR A LARGE ARRAY OF SENSORS 审中-公开

    公开(公告)号：US20190324489A1

    公开(公告)日：2019-10-24

    申请号：US15958741

    申请日：2018-04-20

    Applicant: QUALCOMM Incorporated

    Inventor： Sameer WADHWA ,  Yi WANG ,  Lennart Karl-Axel MATHE

    IPC: G05F3/26 ,  G05F3/24 ,  G06F3/041

    Abstract: In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

    RC OSCILLATOR
    3.
    发明申请
    RC OSCILLATOR 审中-公开
    RC振荡器

    公开(公告)号：US20160087582A1

    公开(公告)日：2016-03-24

    申请号：US14492495

    申请日：2014-09-22

    Applicant: QUALCOMM Incorporated

    Inventor： Lennart Karl-Axel MATHE

    IPC: H03B5/24

    CPC classification number: H03B5/24 ,  H03B5/06

    Abstract: An oscillator includes an oscillating circuit having an input and an output configured to oscillate between a first state and a second state. The oscillating circuit includes a resistor-capacitor circuit configured to bias the oscillating circuit input towards a target voltage. The oscillating circuit is configured to transition the oscillating circuit output from the first state to the second state in response to the oscillating circuit input reaching a threshold voltage before it reaches the target voltage. Another oscillator includes an oscillating circuit having an input and an output configured to oscillate between the first state and the second state. The oscillating circuit is configured to transition the oscillating circuit output from the first state to the second state in response to the oscillating circuit input reaching a threshold voltage. A starting circuit is configured to set the oscillating circuit input to the threshold voltage to start the oscillating circuit.

    Abstract translation: 振荡器包括具有被配置为在第一状态和第二状态之间振荡的输入和输出的振荡电路。 振荡电路包括电阻 - 电容器电路，其被配置为将振荡电路输入偏压到目标电压。 振荡电路被配置为响应于振荡电路输入在达到目标电压之前达到阈值电压，将振荡电路输出从第一状态转换到第二状态。 另一振荡器包括具有输入和配置为在第一状态和第二状态之间振荡的输出的振荡电路。 振荡电路被配置为响应于振荡电路输入达到阈值电压而将振荡电路输出从第一状态转换到第二状态。 启动电路被配置为将振荡电路输入设置为阈值电压以启动振荡电路。

    DYNAMIC HEADROOM FOR ENVELOPE TRACKING
    6.
    发明申请
    DYNAMIC HEADROOM FOR ENVELOPE TRACKING 有权
    动态追踪的动态头饰

    公开(公告)号：US20150002235A1

    公开(公告)日：2015-01-01

    申请号：US14488114

    申请日：2014-09-16

    Applicant: QUALCOMM Incorporated

    Inventor： Lennart Karl-Axel MATHE ,  Pengfei LI ,  Song S. SHI ,  Yunfei SHI ,  Joseph D. RUTKOWSKI

    IPC: H03F1/02 ,  H03F3/21 ,  H03F3/19

    CPC classification number: H03F1/0222 ,  H03F1/0227 ,  H03F3/19 ,  H03F3/21 ,  H03F3/245 ,  H03F2200/102 ,  H03F2200/451

    Abstract: Techniques for dynamically generating a headroom voltage for an envelope tracking system. In an aspect, an initial headroom voltage is updated when a signal from a power amplifier (PA) indicates that the PA headroom is insufficient. The initial headroom voltage may be updated to an operating headroom voltage that includes the initial voltage plus a deficiency voltage plus a margin. In this manner, the operating headroom voltage may be dynamically selected to minimize power consumption while still ensuring that the PA is linear. In a further aspect, a specific exemplary embodiment of a headroom voltage generator using a counter is described.

    Abstract translation: 用于动态产生包络跟踪系统的净空电压的技术。 在一方面，当来自功率放大器（PA）的信号指示PA余量不足时，更新初始余量电压。 初始余量电压可以被更新为包括初始电压加上缺陷电压加上余量的操作净空电压。 以这种方式，可以动态选择操作净空电压以最小化功耗，同时仍然确保PA是线性的。 在另一方面，描述了使用计数器的净空电压发生器的具体示例性实施例。

    LOW-POWER INTER-DIE COMMUNICATION USING DELAY LINES
    7.
    发明公开
    LOW-POWER INTER-DIE COMMUNICATION USING DELAY LINES 审中-公开

    公开(公告)号：US20240056067A1

    公开(公告)日：2024-02-15

    申请号：US18323942

    申请日：2023-05-25

    Applicant: QUALCOMM Incorporated

    Inventor： Sameer WADHWA ,  Lennart Karl-Axel MATHE

    IPC: H03K5/14 ,  H03K5/1534 ,  H03K5/19

    CPC classification number: H03K5/14 ,  H03K5/1534 ,  H03K5/19 ,  H03K5/15033

    Abstract: A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

    BIAS GENERATION AND DISTRIBUTION FOR A LARGE ARRAY OF SENSORS
    9.
    发明申请
    BIAS GENERATION AND DISTRIBUTION FOR A LARGE ARRAY OF SENSORS 审中-公开

    公开(公告)号：US20200050232A1

    公开(公告)日：2020-02-13

    申请号：US16659686

    申请日：2019-10-22

    Applicant: QUALCOMM Incorporated

    Inventor： Sameer WADHWA ,  Yi WANG ,  Lennart Karl-Axel MATHE

    IPC: G05F3/26 ,  G05F3/24 ,  G06F3/041

    Abstract: In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

    OBTAINING ACCURATE TIMING OF ANALOG TO DIGITAL CONVERTER SAMPLES IN CELLULAR MODEM
    10.
    发明公开
    OBTAINING ACCURATE TIMING OF ANALOG TO DIGITAL CONVERTER SAMPLES IN CELLULAR MODEM 审中-公开

    公开(公告)号：US20230336324A1

    公开(公告)日：2023-10-19

    申请号：US17659469

    申请日：2022-04-15

    Applicant: QUALCOMM Incorporated

    Inventor： Lennart Karl-Axel MATHE ,  Brian Clarke BANISTER ,  Christos KOMNINAKIS ,  Minkui LIU

    IPC: H04L7/00 ,  H04W56/00 ,  H03M1/12

    CPC classification number: H04L7/0079 ,  H04W56/005 ,  H03M1/1245

    Abstract: According to embodiments, an example UE may include means for obtaining a set of ADC samples generated by an ADC based on analog signals and an ADC input clock and means for generating, at a first time point, a start signal indicating a starting point of capturing the set of ADC samples. The UE may also include means for synchronizing, at a second time point, the start signal and a system clock and means for generating, at a third time point, a capturing sample clock for capturing the set of ADC samples. The means may further include means for inputting the start signal and the capturing sample clock to a counter to determine a time difference between the second time point and the third time point and means for determining the ADC output timing of the set of ADC samples based on the time difference.

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