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公开(公告)号：US20210099967A1
公开(公告)日：2021-04-01
申请号：US16590022
申请日：2019-10-01
Applicant: QUALCOMM Incorporated
Inventor： Hee Choul LEE , Anilkumar KANERIYA , Minkui LIU , Bok Tae SIM
Abstract: Certain aspects of the present disclosure provide techniques for transceiver timing controls in a synchronized network. A method that may be performed by a user equipment (UE) or a base station (BS) includes determining a first instance of time corresponding to a beginning of a wireless transmission of data by a transceiver, determining a second instance of time corresponding to a beginning of a process configured to load a plurality of buffers with a portion of the data, loading of the plurality of buffers with the data, and transmitting, the data at the first instance of time.
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Patent Agency Ranking
公开(公告)号：US20240223350A1
公开(公告)日：2024-07-04
申请号：US18609676
申请日：2024-03-19
Applicant: QUALCOMM Incorporated
Inventor： Lennart Karl-Axel MATHE , Brian Clarke BANISTER , Christos KOMNINAKIS , Minkui LIU
CPC classification number: H04L7/0079 , H03M1/1245 , H04W56/005
Abstract: An analog-to-digital converter (ADC) has been disclosed. In some implementations, the ADC is configured to generate ADC samples based on input signals and an ADC input clock. The ADC is further configured to generate at a first time point a synchronized start signal indicating a starting point of capturing the ADC samples. The start signal and a system clock can be synchronized at a second time point. At a third time point, a capturing sample clock for capturing the ADC samples is generated. The synchronized start signal and the capturing sample clock can be input to a counter to determine a time difference between the second and third time points. An ADC output timing of the ADC samples can be determined based on the time difference.
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公开(公告)号：US20230336192A1
公开(公告)日：2023-10-19
申请号：US17659468
申请日：2022-04-15
Applicant: QUALCOMM Incorporated
Inventor： Lennart Karl-Axel MATHE , Brian Clarke BANISTER , Christos KOMNINAKIS , Minkui LIU
CPC classification number: H04B1/0007 , H04B1/0053 , H04B1/403 , H04B1/588
Abstract: According to embodiments, an example method for determining an analog-to-digital converter (ADC) output timing in a user equipment may include operating a switch in a first mode to route a system clock from an oscillator to an input of the ADC and determining a first ADC output timing based on a first set of ADC samples generated by the ADC. The method may also include operating the switch in a second mode to route analog signals from a transceiver of the user equipment to the input of the ADC and obtaining a second set of ADC samples generated by the ADC based on the analog signals.
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公开(公告)号：US20160255639A1
公开(公告)日：2016-09-01
申请号：US15031220
申请日：2014-11-20
Applicant: QUALCOMM Incorporated
Inventor： Qingxin CHEN , Minkui LIU , Francis Ming-Meng NGAI , Shanshan WANG , Chinmway S. VAZE , Insung KANG , Tom CHIN , Wei ZHANG , Zhibin DANG , Xiaoning LU , Abhijit YESHWANTPUR , Baris EFE , Michael Lee MCCLOUD
CPC classification number: H04W72/082 , H04W72/02 , H04W72/0446 , H04W72/1215 , H04W72/1231 , H04W88/06
Abstract: The present methods and apparatus relate to interference mitigation at a user equipment during wireless communication, comprising determining that a first portion of a first radio access technology (RAT) activity scheduled during a first time slot overlaps in duration with a second portion of a second RAT activity scheduled during a second time slot; excluding the first portion of the first RAT activity based at least in part on determining that the first portion of the first RAT activity overlaps in duration with the second portion of the second RAT activity; and performing a non-overlap portion of the first RAT activity during the first time slot, wherein the non-overlap portion of the first RAT activity is a portion of the first RAT activity that remains after excluding of the first portion of the first RAT activity.
Abstract translation: 本方法和装置涉及在无线通信期间在用户设备处的干扰减轻，包括确定在第一时隙期间调度的第一无线电接入技术（RAT）活动的第一部分在持续时间内与第二RAT的第二部分重叠 在第二时间段安排的活动; 至少部分地基于确定第一RAT活动的第一部分与第二RAT活动的第二部分的持续时间重叠，排除第一RAT活动的第一部分; 以及在所述第一时隙期间执行所述第一RAT活动的非重叠部分，其中所述第一RAT活动的所述非重叠部分是在排除所述第一RAT活动的所述第一部分之后保留的所述第一RAT活动的一部分 。
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公开(公告)号：US20230417870A1
公开(公告)日：2023-12-28
申请号：US17808745
申请日：2022-06-24
Applicant: QUALCOMM Incorporated
Inventor： Tharun Adithya SRIKRISHNAN , Intae KANG , Supratik BHATTACHARJEE , Christos KOMNINAKIS , Michael Lee MCCLOUD , Gautham HARIHARAN , Minkui LIU , Gary John BALLANTYNE
CPC classification number: G01S7/4008 , G01S13/42
Abstract: Certain aspects of the present disclosure provide techniques for identifying a minimal, or at least reduced, set of representative calibration paths in radio frequency (RF) circuits and calibrating other calibration paths based on calibration codes used for the representative calibration paths. An example method generally includes receiving a calibration data set including measurements associated with each calibration path of a plurality of calibration paths in an RF circuit. Based on a clustering model and the calibration data set, a plurality of calibration clusters is generated. From each respective calibration cluster of the plurality of calibration clusters, a respective representative calibration path for is selected for the respective calibration cluster. Generally, calibration codes generated for the representative calibration path are applicable to other calibration paths in the calibration cluster. A lookup table is generated associating a respective calibration path with other calibration paths in each respective calibration cluster.
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公开(公告)号：US20230336324A1
公开(公告)日：2023-10-19
申请号：US17659469
申请日：2022-04-15
Applicant: QUALCOMM Incorporated
Inventor： Lennart Karl-Axel MATHE , Brian Clarke BANISTER , Christos KOMNINAKIS , Minkui LIU
CPC classification number: H04L7/0079 , H04W56/005 , H03M1/1245
Abstract: According to embodiments, an example UE may include means for obtaining a set of ADC samples generated by an ADC based on analog signals and an ADC input clock and means for generating, at a first time point, a start signal indicating a starting point of capturing the set of ADC samples. The UE may also include means for synchronizing, at a second time point, the start signal and a system clock and means for generating, at a third time point, a capturing sample clock for capturing the set of ADC samples. The means may further include means for inputting the start signal and the capturing sample clock to a counter to determine a time difference between the second time point and the third time point and means for determining the ADC output timing of the set of ADC samples based on the time difference.
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