AUTOMATIC FAILURE IDENTIFICATION AND FAILURE PATTERN IDENTIFICATION WITHIN AN IC WAFER

    公开(公告)号:US20170242070A1

    公开(公告)日:2017-08-24

    申请号:US15051537

    申请日:2016-02-23

    Abstract: Embodiments described herein provide a method for identifying failure patterns in electronic devices. The method begins when a limit is determined for a parameter of interest. A series of the electronic devices is then tested using the limit of the parameter of interest. Failing devices are then identified and x and y coordinate values are plotted. Pattern recognition may be used to determine if the failures shown on the coordinate plot fit a failure pattern. The limit of the parameter of interest is then regressed in steps to the mean value of the failing devices and the electronic devices are retested. The failure pattern of the retested devices is examined to determine if the failure pattern fits a failure pattern. If the failure pattern fits a failure pattern then the parameter of interest may be found to affect the yield rate of production for the electronic devices.

    Algorithm for preferred core sequencing to maximize performance and reduce chip temperature and power
    2.
    发明授权
    Algorithm for preferred core sequencing to maximize performance and reduce chip temperature and power 有权
    优化核心测序的算法可最大限度地提高性能并降低芯片的温度和功率

    公开(公告)号:US09557797B2

    公开(公告)日:2017-01-31

    申请号:US14319393

    申请日:2014-06-30

    Abstract: Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core.

    Abstract translation: 方面包括用于为计算设备的状态选择优选处理器核心组合的计算设备,系统和方法。 在一方面,可以确定包含多核处理器的计算设备的状态。 可以通过将处理器核心的当前泄漏与其他处理器核心的当前泄漏进行比较来确定多个电流泄漏比。 可以将这些比率与各个不等式中的计算装置的状态的边界进行比较。 响应于确定相应的不等式是真实的,可以选择与多个边界相关联的处理器核心。 边界可以与被认为对于计算设备的相关状态优选的一组处理器核心相关联。 存在于真正不等式的每个边界的处理器核心集合中的处理器核心可以是所选择的处理器核心。

    Algorithm For Preferred Core Sequencing To Maximize Performance And Reduce Chip Temperature And Power
    3.
    发明申请
    Algorithm For Preferred Core Sequencing To Maximize Performance And Reduce Chip Temperature And Power 有权
    优化核心排序的算法以最大限度地提高性能并降低芯片温度和功率

    公开(公告)号:US20150338902A1

    公开(公告)日:2015-11-26

    申请号:US14319393

    申请日:2014-06-30

    Abstract: Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core.

    Abstract translation: 方面包括用于为计算设备的状态选择优选处理器核心组合的计算设备,系统和方法。 在一方面,可以确定包含多核处理器的计算设备的状态。 可以通过将处理器核心的当前泄漏与其他处理器核心的当前泄漏进行比较来确定多个电流泄漏比。 可以将这些比率与各个不等式中的计算装置的状态的边界进行比较。 响应于确定相应的不等式是真实的,可以选择与多个边界相关联的处理器核心。 边界可以与被认为对于计算设备的相关状态优选的一组处理器核心相关联。 存在于真正不等式的每个边界的处理器核心集合中的处理器核心可以是所选择的处理器核心。

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