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    Algorithm for preferred core sequencing to maximize performance and reduce chip temperature and power
    2.
    发明授权
    Algorithm for preferred core sequencing to maximize performance and reduce chip temperature and power 有权
    优化核心测序的算法可最大限度地提高性能并降低芯片的温度和功率

    公开(公告)号：US09557797B2

    公开(公告)日：2017-01-31

    申请号：US14319393

    申请日：2014-06-30

    Applicant: QUALCOMM Incorporated

    Inventor： Rajat Mittal ,  Mehdi Saeidi ,  Tao Xue ,  Ronald Frank Alton ,  Rajit Chandra ,  Sachin Dasnurkar

    IPC: G06F1/32 ,  G06F9/50

    CPC classification number: G06F1/3234 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/22 ,  Y02D10/24

    Abstract: Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core.

    Abstract translation: 方面包括用于为计算设备的状态选择优选处理器核心组合的计算设备，系统和方法。 在一方面，可以确定包含多核处理器的计算设备的状态。 可以通过将处理器核心的当前泄漏与其他处理器核心的当前泄漏进行比较来确定多个电流泄漏比。 可以将这些比率与各个不等式中的计算装置的状态的边界进行比较。 响应于确定相应的不等式是真实的，可以选择与多个边界相关联的处理器核心。 边界可以与被认为对于计算设备的相关状态优选的一组处理器核心相关联。 存在于真正不等式的每个边界的处理器核心集合中的处理器核心可以是所选择的处理器核心。

    Algorithm For Preferred Core Sequencing To Maximize Performance And Reduce Chip Temperature And Power
    3.
    发明申请
    Algorithm For Preferred Core Sequencing To Maximize Performance And Reduce Chip Temperature And Power 有权
    优化核心排序的算法以最大限度地提高性能并降低芯片温度和功率

    公开(公告)号：US20150338902A1

    公开(公告)日：2015-11-26

    申请号：US14319393

    申请日：2014-06-30

    Applicant: QUALCOMM Incorporated

    Inventor： Rajat MITTAL ,  Mehdi Saeidi ,  Tao Xue ,  Ronald Frank Alton ,  Rajit Chandra ,  Sachin Dasnurkar

    IPC: G06F1/32

    CPC classification number: G06F1/3234 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/22 ,  Y02D10/24

    Abstract: Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core.

    Abstract translation: 方面包括用于为计算设备的状态选择优选处理器核心组合的计算设备，系统和方法。 在一方面，可以确定包含多核处理器的计算设备的状态。 可以通过将处理器核心的当前泄漏与其他处理器核心的当前泄漏进行比较来确定多个电流泄漏比。 可以将这些比率与各个不等式中的计算装置的状态的边界进行比较。 响应于确定相应的不等式是真实的，可以选择与多个边界相关联的处理器核心。 边界可以与被认为对于计算设备的相关状态优选的一组处理器核心相关联。 存在于真正不等式的每个边界的处理器核心集合中的处理器核心可以是所选择的处理器核心。

    SYSTEM AND METHOD OF MONITORING A CENTRAL PROCESSING UNIT IN REAL TIME
    4.
    发明申请
    SYSTEM AND METHOD OF MONITORING A CENTRAL PROCESSING UNIT IN REAL TIME 有权
    实时监控中央处理单元的系统及方法

    公开(公告)号：US20130061069A1

    公开(公告)日：2013-03-07

    申请号：US13668764

    申请日：2012-11-05

    Applicant: Qualcomm Incorporated

    Inventor： Steven S. Thomson ,  Ali Iranli ,  Michael J. Drop ,  Vinodh R. Cuppu ,  Christopher Kong Yee Chun ,  Tao Xue ,  Haw-Jing Lo ,  Moinul H. Khan

    IPC: G06F1/26

    CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: Devices and methods for monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

    Abstract translation: 公开了用于实时监控一个或多个中央处理单元的装置和方法。 该方法可以包括：实时地监视与一个或多个CPU相关联的状态数据，过滤状态数据，并且至少部分地基于经过滤的状态数据，选择性地改变一个或多个系统设置。 设备可以包括用于实时监视与一个或多个CPU相关联的状态数据的装置，用于过滤状态数据的装置，以及用于至少部分地基于经过滤的状态数据选择性地改变一个或多个系统设置的装置。 设备还可以包括子采样电路，其被配置为从中央处理单元接收硬件核心信号并输出​​中央处理单元状态指示，以及无限脉冲响应滤波器，连接到子采样电路并被配置为接收中央 来自子采样电路的处理单元状态指示。

    System and method of monitoring a central processing unit in real time
    6.
    发明授权
    System and method of monitoring a central processing unit in real time 有权
    实时监控中央处理单元的系统和方法

    公开(公告)号：US09086877B2

    公开(公告)日：2015-07-21

    申请号：US13668764

    申请日：2012-11-05

    Applicant: QUALCOMM Incorporated

    Inventor： Steven S. Thomson ,  Ali Iranli ,  Michael J. Drop ,  Vinodh R. Cuppu ,  Christopher Kong Yee Chun ,  Tao Xue ,  Haw-Jing Lo ,  Moinul H. Khan

    IPC: G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: Devices and methods for monitoring one or more central processing units in real time are disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

    Abstract translation: 公开了实时监控一个或多个中央处理单元的装置和方法。 该方法可以包括：实时地监视与一个或多个CPU相关联的状态数据，过滤状态数据，并且至少部分地基于经过滤的状态数据，选择性地改变一个或多个系统设置。 设备可以包括用于实时监视与一个或多个CPU相关联的状态数据的装置，用于过滤状态数据的装置，以及用于至少部分地基于经过滤的状态数据选择性地改变一个或多个系统设置的装置。 设备还可以包括子采样电路，其被配置为从中央处理单元接收硬件核心信号并输出​​中央处理单元状态指示，以及无限脉冲响应滤波器，连接到子采样电路并被配置为接收中央 来自子采样电路的处理单元状态指示。

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