公开(公告)号：US20220066955A1

公开(公告)日：2022-03-03

申请号：US17005143

申请日：2020-08-27

Applicant: QUALCOMM Incorporated

Inventor： Sharon GRAIF ,  Navdeep MER ,  Lior AMARILIO

IPC: G06F13/16 ,  G06F1/28 ,  G06F11/07 ,  G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and apparatus are configured to enable a receiver to provide feedback. A feedback mechanism enables a transmitting device to identify the provider of feedback for a multicast transmission, and the feedback transmitted by one or more individual receivers of the multicast transmission. A method includes receiving a multicast write command from the serial bus in a first datagram, writing a data byte received in a first data frame of the first datagram to a register address identified by the first datagram, and providing device-specific feedback regarding the first datagram in a multibit slot within the second data frame. The multibit slot is one of a plurality of sequential multibit slots defined for the second data frame. Each multibit slot in the plurality of sequential multibit slots may provide device-specific feedback from one receiving device addressed by the multicast write command.

公开(公告)号：US20190171609A1

公开(公告)日：2019-06-06

申请号：US16162536

申请日：2018-10-17

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Radu PITIGOI-ARON ,  Richard Dominic WIETFELDT ,  Sharon GRAIF

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/16 ,  G06F13/40

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method for transmitting data over a serial bus having multiple data lanes includes providing a plurality of frames, each frame being configured to carry up to a maximum number of data bytes, transmitting a first frame over the serial bus, where the first frame is filled with first data bytes, notifying one or more devices of unavailability of an alert opportunity prior to transmitting the first frame, transmitting a second frame over the serial bus, where the first frame includes second data bytes less in number than the maximum number of data bytes, and notifying the one or more devices that the second frame provides an opportunity to launch an alert after transmission of the second data bytes.

公开(公告)号：US20190129464A1

公开(公告)日：2019-05-02

申请号：US16162564

申请日：2018-10-17

Applicant: QUALCOMM Incorporated

Inventor： Sharon GRAIF ,  Oren NISHRY ,  Shay MASWARI

IPC: G06F1/08 ,  G06F13/42

Abstract: System, methods and apparatus are described that enable the reliable generation of pulses in a clock signal transmitted over an I3C bus. In various aspects of the disclosure, a method of data communications may be performed by a master device to generate a clock signal to be transmitted on a serial bus. The method includes calculating a divisor based on frequency of a first clock signal and duration of a first pulse to be transmitted in a second clock signal over a clock line of the serial bus, using the divisor to divide the first clock signal to obtain a divided clock signal, and generating the first pulse using the divided clock signal.

公开(公告)号：US20190018818A1

公开(公告)日：2019-01-17

申请号：US16008509

申请日：2018-06-14

Applicant: QUALCOMM Incorporated

Inventor： Sharon GRAIF ,  Radu PITIGOI-ARON ,  Lior AMARILIO

IPC: G06F13/42 ,  G06F13/26 ,  G06F13/40 ,  G06F13/36

Abstract: Systems, methods, and apparatus for communication over a serial bus in accordance with an I3C protocol are described that enable a non-participating device to cause a master device on an I3C bus transmit a STOP condition that terminates a transaction with a slave device coupled to the I3C bus. A method performed at a master device coupled to a serial bus includes initiating a transaction between the master device and a first slave device, terminating the transaction before completion of the transaction when a second slave device intervenes in the transaction, and servicing the second slave device after terminating the transaction. The transaction may include transmissions of data frames over the serial bus. The second slave device may intervene when it is not a party to the transaction.

公开(公告)号：US20230350841A1

公开(公告)日：2023-11-02

申请号：US17923110

申请日：2021-04-16

Applicant: QUALCOMM Incorporated

Inventor： Sharon GRAIF ,  Navdeep MER ,  Naveen Kumar NARALA ,  Sriharsha CHAKKA

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F13/4072

Abstract: Systems, methods, and apparatus are configured to enable a receiver to provide feedback. In one example, a method performed at a device coupled to a serial bus includes receiving a write command from the serial bus in a datagram, writing a data byte received in a first data frame of the datagram to a register address identified by the datagram, and using a second data frame of the datagram to provide feedback regarding the datagram. Feedback may be provided by driving a data line of the serial bus to provide a negative acknowledgement during the second data frame when a transmission error is detected in the datagram, and refraining from driving the data line of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing an acknowledgement of the datagram.

公开(公告)号：US20210152620A1

公开(公告)日：2021-05-20

申请号：US16688377

申请日：2019-11-19

Applicant: QUALCOMM Incorporated

Inventor： Lior AMARILIO ,  Sharon GRAIF ,  Yiftach BENJAMINI

IPC: H04L29/06 ,  H04L12/40 ,  H04S1/00

Abstract: In some aspects, the present disclosure provides a method for communicating audio data. In one example, the method includes determining whether a condition for each transport opportunity on an audio channel is met based on an audio sample rate and a channel rate of the audio channel. For each transport opportunity, upon determining that the condition is met for the transport opportunity, the method also includes transmitting audio sample data over the transport opportunity or receiving audio sample data at the transport opportunity.

公开(公告)号：US20180373659A1

公开(公告)日：2018-12-27

申请号：US16012532

申请日：2018-06-19

Applicant: QUALCOMM Incorporated

Inventor： Lior AMARILIO ,  Amit GIL ,  Sharon GRAIF

IPC: G06F13/364 ,  G06F1/08 ,  G06F3/16 ,  H04R3/00 ,  H04R3/12

Abstract: System, methods and apparatus are described that can improve available bandwidth on a SoundWire bus without increasing the number of pins used by the SoundWire bus. A method performed at a master device coupled to a SoundWire bus includes providing a clock signal by a first master device over a clock line of a SoundWire bus to a first slave device and a second slave device coupled to the SoundWire bus, transmitting first control information from the first master device to the first slave device over a first data line of the SoundWire bus, and transmitting second control information from the first master device to the second slave device over a second data line of the SoundWire bus. The first control information may be different from the second control information and is transmitted concurrently with the second control information.

公开(公告)号：US20220358079A1

公开(公告)日：2022-11-10

申请号：US17307842

申请日：2021-05-04

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Radu PITIGOI-ARON ,  Sharon GRAIF ,  Lior AMARILIO ,  Richard Dominic WIETFELDT

IPC: G06F13/42 ,  G06F1/08 ,  G06F13/20

Abstract: Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.

公开(公告)号：US20200241070A1

公开(公告)日：2020-07-30

申请号：US16262550

申请日：2019-01-30

Applicant: QUALCOMM Incorporated

Inventor： Punit KISHORE ,  Tomer Rafael BEN-CHEN ,  Sharon GRAIF

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/28 ,  G06F13/42

Abstract: A method of in-system structural testing of a system-on-chip (SoC) using a peripheral interface port is described. The method including enabling a scan interface controller of the SoC through the peripheral interface port. The method also includes streaming structural test patterns in the SoC through the scan interface controller.

公开(公告)号：US20190356412A1

公开(公告)日：2019-11-21

申请号：US16381415

申请日：2019-04-11

Applicant: QUALCOMM Incorporated

Inventor： Radu PITIGOI-ARON ,  Sharon GRAIF ,  Richard Dominic WIETFELDT

IPC: H04L1/00 ,  G06F13/42

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes providing a data payload for a data frame to be transmitted over a plurality of data lanes of a multilane serial bus, providing a preamble to precede the data payload in transmission over the multilane serial bus, configuring one or more repurposed bit fields in the data frame to indicate that a multi-bit cyclic redundancy check is provided in the data frame, and transmitting the data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus. At least one bit of the multi-bit cyclic redundancy check is transmitted on two or more data lanes of the plurality of data lanes.