公开(公告)号：US20070057411A1

公开(公告)日：2007-03-15

申请号：US11518691

申请日：2006-09-11

申请人： R. Williams ,  Thomas Woods

发明人： R. Williams ,  Thomas Woods

IPC分类号： H05H1/26 ,  H01J7/24

CPC分类号： B29C59/14 ,  B29B13/00 ,  B29B13/08 ,  B29K2105/251 ,  H01J37/32431 ,  H05H2245/121

摘要： Apparatus and a method is disclosed for treating particulate materials (e.g., plastic resins) so as change the surface characteristics of the particulate materials comprising a work chamber receiving a quantity of the particulate material to be treated, a power supply, and a capacitor energized by the power supply, where the capacitor generates a capacitive plasma which is used to treat the particulate material such that when objects are formed from the treated particulate material, such objects will have enhanced surface characteristics. Further, a quantity of a gas may be introduced within the work chamber to facilitate the generation of a plasma within the particulate material.

摘要翻译： 公开了用于处理颗粒材料（例如，塑料树脂）的装置和方法，以便改变包括接收一定量待处理的颗粒材料的工作室的颗粒材料的表面特性，电源和由 电源，其中电容器产生用于处理颗粒材料的电容等离子体，使得当从被处理的颗粒材料形成物体时，这些物体将具有增强的表面特性。 此外，一定量的气体可以被引入到工作室内以便于在颗粒材料内产生等离子体。

公开(公告)号：US20070254377A1

公开(公告)日：2007-11-01

申请号：US11413516

申请日：2006-04-28

申请人： Zhiyong Li ,  William Tong ,  R. Williams

发明人： Zhiyong Li ,  William Tong ,  R. Williams

IPC分类号： G01N21/62

CPC分类号： G01N21/658 ,  Y10T428/218 ,  Y10T428/28

摘要： Packaged NERS-active structures are disclosed that include a NERS substrate having a NERS-active structure thereon, and a packaging substrate over the NERS substrate having an opening therethrough, the opening in alignment with the NERS-active structure. A membrane may cover the opening in the packaging substrate. In order to perform nanoenhanced Raman spectroscopy, the membrane may be removed, and an analyte placed on the NERS substrate adjacent the NERS-active structure. The membrane may be replaced with another membrane after the analyte has been placed on the substrate. The membrane may maintain the pristine state of the substrate before it is deployed, and the replacement membrane may preserve the substrate and analyte for archival purposes. Also disclosed are methods for performing NERS with packaged NERS-active structures.

摘要翻译： 公开了封装的NERS-活性结构，其包括其上具有NERS-活性结构的NERS衬底和在NERS衬底上的具有穿过其中的开口的封装衬底，该开口与NERS-活性结构对准。 膜可以覆盖封装衬底中的开口。 为了进行纳米增强拉曼光谱，可以去除膜，并将分析物放置在邻近NERS-活性结构的NERS衬底上。 在将分析物放置在基底上之后，膜可以用另一膜替代。 膜可以在其被部署之前保持基材的原始状态，并且替换膜可以保留底物和分析物用于归档目的。 还公开了使用封装的NERS-活性结构来执行NERS的方法。

公开(公告)号：US20070205483A1

公开(公告)日：2007-09-06

申请号：US11701086

申请日：2007-01-31

申请人： R. Williams ,  Gregory Snider ,  Duncan Stewart

发明人： R. Williams ,  Gregory Snider ,  Duncan Stewart

IPC分类号： H01L29/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  G11C2213/81 ,  H01H1/0094 ,  H01L27/285 ,  H01L29/0673 ,  H01L29/0676 ,  H01L51/0591 ,  H01L51/0595

摘要： Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer. Pins can be configured according to any periodic tiling of the microscale layer.

摘要翻译： 本发明的实施例涉及包括在集成电路和其他电子设备中的混合比例电子接口，其提供主要是微米级或亚微米级的微尺度特征之间的密集电互连以及主要为纳米尺度层的纳米尺度特征。 在本发明的一个实施方案中，主要是纳米尺度层包括通过平行的，紧密间隔的纳米线束组之间的纳米线结密合地互连的亚微米级或微米级的镶嵌图案。 主要是亚微米级或微尺度层包括与主要是纳米级层中的亚微米级或微尺度焊盘互补定位的引脚。 引脚可以根据微层的任何周期性平铺进行配置。

公开(公告)号：US20070086002A1

公开(公告)日：2007-04-19

申请号：US11252146

申请日：2005-10-17

申请人： M. Islam ,  Shih-Yuan Wang ,  R. Williams

发明人： M. Islam ,  Shih-Yuan Wang ,  R. Williams

IPC分类号： G01J3/44 ,  G01N21/65

CPC分类号： G01N21/658 ,  Y10S977/786

摘要： A system for performing nanostructure-enhanced Raman spectroscopy (NERS) includes a radiation source, a radiation detector configured to detect Raman scattered radiation scattered by an analyte, and a container configured to provide a sealed enclosure. The NERS system further includes a turbulence generating device configured to generate random dynamic motion of a plurality of nanoparticles within the container. A method for performing NERS includes providing a container configured to provide a sealed enclosure, providing a plurality of nanoparticles each comprising a NERS-active material and an analyte within the container, causing random dynamic motion of the plurality of nanoparticles and the analyte, irradiating the plurality of nanoparticles and the analyte with radiation, and detecting Raman scattered radiation scattered by the analyte.

摘要翻译： 用于执行纳米结构增强拉曼光谱（NERS）的系统包括辐射源，被配置为检测被分析物散射的拉曼散射辐射的辐射检测器和被配置为提供密封外壳的容器。 NERS系统还包括被配置成产生容器内的多个纳米颗粒的随机动态运动的湍流产生装置。 一种用于执行NERS的方法包括提供一种被配置成提供密封外壳的容器，提供多个纳米颗粒，每个纳米颗粒包含在容器内的NERS-活性材料和分析物，引起多个纳米颗粒和分析物的随机动态运动， 多个纳米颗粒和分析物与辐射，并检测被分析物散射的拉曼散射辐射。

公开(公告)号：US20070066070A1

公开(公告)日：2007-03-22

申请号：US11601084

申请日：2006-11-16

申请人： M. Islam ,  Gun Jung ,  Yong Chen ,  R. Williams

发明人： M. Islam ,  Gun Jung ,  Yong Chen ,  R. Williams

IPC分类号： H01L21/465

CPC分类号： H01L21/76838 ,  H01L21/0337

摘要： An imprinting apparatus and method of fabrication provide a mold having a pattern for imprinting. The apparatus includes a semiconductor substrate polished in a [110] direction. The semiconductor substrate has a (110) horizontal planar surface and vertical sidewalls of a wet chemical etched trench. The sidewalls are aligned with and therefore are (111) vertical lattice planes of the semiconductor substrate. The semiconductor substrate includes a plurality of vertical structures between the sidewalls, wherein the vertical structures may be nano-scale spaced apart. The method includes wet etching a trench with spaced apart (111) vertical sidewalls in an exposed portion of the (110) horizontal surface of the semiconductor substrate along (111) vertical lattice planes. A chemical etching solution is used that etches the (111) vertical lattice planes slower than the (110) horizontal lattice plane. The method further includes forming the imprinting mold.

摘要翻译： 压印装置和制造方法提供具有用于压印的图案的模具。 该装置包括沿[110]方向抛光的半导体衬底。 半导体衬底具有（110）水平平面和湿化学蚀刻沟槽的垂直侧壁。 侧壁与半导体衬底对准并且因此是（111）垂直的晶格面。 半导体衬底包括在侧壁之间的多个垂直结构，其中垂直结构可以是纳米级隔开的。 该方法包括在（111）垂直晶格面的半导体衬底的（110）水平表面的暴露部分中湿式蚀刻具有间隔开（111）垂直侧壁的沟槽。 使用蚀刻比（110）水平晶格面慢的（111）垂直晶格面的化学蚀刻溶液。 该方法还包括形成压印模具。

公开(公告)号：US20060240681A1

公开(公告)日：2006-10-26

申请号：US11114307

申请日：2005-04-25

申请人： R. Williams ,  Philip Kuekes

发明人： R. Williams ,  Philip Kuekes

IPC分类号： H01L21/00

CPC分类号： H04L49/40 ,  B82Y10/00 ,  G11C13/02 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/81 ,  H04L49/101 ,  Y10S977/762 ,  Y10S977/767

摘要： Various embodiments of the present invention include three-dimensional, at least partially nanoscale, electronic circuits and devices in which signals can be routed in three independent directions, and in which electronic components can be fabricated at junctions interconnected by internal signal lines. The three-dimensional, at least partially nanoscale, electronic circuits and devices include layers, the nanowire or microscale-or-submicroscale/nanowire junctions of each of which may be economically and efficiently fabricated as one type of electronic component. Various embodiments of the present invention include nanoscale memories, nanoscale programmable arrays, nanoscale multiplexers and demultiplexers, and an almost limitless number of specialized nanoscale circuits and nanoscale electronic components.

摘要翻译： 本发明的各种实施例包括三维，至少部分纳米级的电子电路和装置，其中信号可以在三个独立的方向上布线，并且其中电子部件可以在通过内部信号线互连的连接点处制造。 三维，至少部分纳米级的电子电路和器件包括层，其中每一个的纳米线或微米级或亚微米级/纳米线结可以经济地和有效地制造为一种类型的电子部件。 本发明的各种实施例包括纳米级存储器，纳米级可编程阵列，纳米级多路复用器和解复用器，以及几乎无限数量的专用纳米尺度电路和纳米级电子部件。

公开(公告)号：US20070252128A1

公开(公告)日：2007-11-01

申请号：US11414578

申请日：2006-04-28

申请人： R. Williams ,  Zhiyong Li ,  Douglas Ohlberg ,  Philip Kuekes ,  Duncan Stewart

发明人： R. Williams ,  Zhiyong Li ,  Douglas Ohlberg ,  Philip Kuekes ,  Duncan Stewart

IPC分类号： H01L29/02 ,  H01L47/00

CPC分类号： G11C13/02 ,  G11C13/0009 ,  G11C2213/77 ,  H01L51/0591

摘要： A switching device includes at least one bottom electrode and at least one top electrode. The top electrode crosses the bottom electrode at a non-zero angle, thereby forming a junction. A metal oxide layer is established on at least one of the bottom electrode or the top electrode. A molecular layer including a monolayer of organic molecules and a source of water molecules is established in the junction. Upon introduction of a forward bias, the molecular layer facilitates a redox reaction between the electrodes, thereby reducing a tunneling gap between the electrodes.

摘要翻译： 开关装置包括至少一个底部电极和至少一个顶部电极。 顶部电极以非零角度穿过底部电极，从而形成结。 在底电极或顶电极中的至少一个上建立金属氧化物层。 在连接处建立了包括有机分子单层和水分子源的分子层。 在引入正向偏压时，分子层促进电极之间的氧化还原反应，从而减少电极之间的隧道间隙。

公开(公告)号：US20070176168A1

公开(公告)日：2007-08-02

申请号：US11342076

申请日：2006-01-27

申请人： Gregory Snider ,  R. Williams

发明人： Gregory Snider ,  R. Williams

IPC分类号： H01L29/08

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  G11C2213/81 ,  H01H1/0094 ,  H01L27/285 ,  H01L29/0673 ,  H01L29/0676 ,  H01L51/0591 ,  H01L51/0595

摘要： Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer.

摘要翻译： 本发明的实施例涉及包括在集成电路和其他电子设备中的混合比例电子接口，其提供主要是微米级或亚微米级的微尺度特征之间的密集电互连以及主要为纳米尺度层的纳米尺度特征。 在本发明的一个实施方案中，主要是纳米尺度层包括通过平行的，紧密间隔的纳米线束组之间的纳米线结密合地互连的亚微米级或微米级的镶嵌图案。 主要是亚微米级或微尺度层包括与主要是纳米级层中的亚微米级或微尺度焊盘互补定位的引脚。

公开(公告)号：US20070154129A1

公开(公告)日：2007-07-05

申请号：US11127542

申请日：2005-05-11

申请人： Raymond Beausoleil ,  Philip Kuekes ,  R. Williams

发明人： Raymond Beausoleil ,  Philip Kuekes ,  R. Williams

IPC分类号： G02B6/00

CPC分类号： G01N21/7703 ,  G01N21/648 ,  G01N21/65 ,  G01N21/94 ,  G01N33/569 ,  G01N35/00871 ,  G01N2021/7786 ,  G01N2035/00881

摘要： A sensor includes traps that are adjacent to a waveguide and capable of holding a contaminant for an interaction with an evanescent field surrounding the waveguide. When held in a trap, a particle of the contaminant, which may be an atom, a molecule, a virus, or a microbe, scatters light from the waveguide, and the scattered light can be measured to detect the presence or concentration of the contaminant. Holding of the particles permits sensing of the contaminant in a gas where movement of the particles might otherwise be too fast to permit measurement of the interaction with the evanescent field. The waveguide, a lighting system for the waveguide, a photosensor, and a communications interface can all be fabricated on a semiconductor die to permit fabrication of an autonomous nanosensor capable of suspension in the air or a gas being sensed.

摘要翻译： 传感器包括与波导相邻并且能​​够保持污染物以与与波导周围的ev逝场相互作用的阱。 当保持在陷阱中时，可能是原子，分子，病毒或微生物的污染物的颗粒散射来自波导的光，并且可以测量散射光以检测污染物的存在或浓度 。 保持颗粒允许感测气体中的污染物，其中颗粒的移动可能太快以至于不能测量与渐逝场的相互作用。 波导，用于波导的照明系统，光传感器和通信接口都可以在半导体管芯上制造，以允许制造能够在空气中悬浮的自主纳米传感器或被感测的气体。

公开(公告)号：US20070053378A1

公开(公告)日：2007-03-08

申请号：US11221036

申请日：2005-09-06

申请人： Philip Kuekes ,  J. Roblnett ,  Ron Roth ,  Gadlel Seroussl ,  Gregory Smider ,  R. Williams

发明人： Philip Kuekes ,  J. Roblnett ,  Ron Roth ,  Gadlel Seroussl ,  Gregory Smider ,  R. Williams

IPC分类号： H04J15/00

CPC分类号： G11C8/10 ,  B82Y10/00 ,  G11C13/00 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/77 ,  G11C2213/81

摘要： Various embodiments of the present invention include methods for determining nanowire addressing schemes and include microscale/nanoscale electronic devices that incorporate the nanowire addressing schemes for reliably addressing nanowire-junctions within nanowire crossbars. The addressing schemes allow for change in the resistance state, or other physical or electronic state, of a selected nanowire-crossbar junction without changing the resistance state, or other physical or electronic state, of the remaining nanowire-crossbar junctions, and without destruction of either the selected nanowire-crossbar junction or the remaining, non-selected nanowire-crossbar junctions. Additional embodiments of the present invention include nanoscale memory arrays and other nanoscale electronic devices that incorporate the nanowire-addressing-scheme embodiments of the present invention. Certain of the embodiments of the present invention employ constant-weight codes, a well-known class of error-control-encoding codes, as addressed-nanowire selection voltages applied to microscale output signal lines of microscale/nanoscale encoder-demultiplexers that are selectively interconnected with a set of nanowires.

摘要翻译： 本发明的各种实施例包括用于确定纳米线寻址方案的方法，并且包括微纳米级纳米级电子器件，其纳入用于在纳米线交叉管内可靠地寻址纳米线结的纳米线寻址方案。 寻址方案允许选择的纳米线 - 交叉连接点的电阻状态或其他物理或电子状态的改变，而不改变剩余的纳米线 - 交叉连接点的电阻状态或其他物理或电子状态，并且不破坏 选择的纳米线 - 交叉结或剩余的未选择的纳米线交叉点结。 本发明的另外的实施例包括结合本发明的纳米线寻址方案实施例的纳米级存储器阵列和其它纳米级电子器件。 本发明的某些实施例采用常规权重代码，众所周知的错误控制编码代码，作为施加到微尺度/纳米级编码器 - 解复用器的微量输出信号线上的寻址纳米线选择电压，其被选择性地互连 与一套纳米线。