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    Mixed-scale electronic interface
    1.
    发明申请
    Mixed-scale electronic interface 有权
    混合电子接口

    公开(公告)号：US20070205483A1

    公开(公告)日：2007-09-06

    申请号：US11701086

    申请日：2007-01-31

    申请人： R. Williams ,  Gregory Snider ,  Duncan Stewart

    发明人： R. Williams ,  Gregory Snider ,  Duncan Stewart

    IPC分类号： H01L29/00

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  G11C2213/81 ,  H01H1/0094 ,  H01L27/285 ,  H01L29/0673 ,  H01L29/0676 ,  H01L51/0591 ,  H01L51/0595

    摘要： Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer. Pins can be configured according to any periodic tiling of the microscale layer.

    摘要翻译： 本发明的实施例涉及包括在集成电路和其他电子设备中的混合比例电子接口，其提供主要是微米级或亚微米级的微尺度特征之间的密集电互连以及主要为纳米尺度层的纳米尺度特征。 在本发明的一个实施方案中，主要是纳米尺度层包括通过平行的，紧密间隔的纳米线束组之间的纳米线结密合地互连的亚微米级或微米级的镶嵌图案。 主要是亚微米级或微尺度层包括与主要是纳米级层中的亚微米级或微尺度焊盘互补定位的引脚。 引脚可以根据微层的任何周期性平铺进行配置。

    NANOSCALE LATCH-ARRAY PROCESSING ENGINES
    2.
    发明申请
    NANOSCALE LATCH-ARRAY PROCESSING ENGINES 有权
    NANOSCALE LATCH-ARRAY加工发动机

    公开(公告)号：US20070109014A1

    公开(公告)日：2007-05-17

    申请号：US11192197

    申请日：2005-07-27

    申请人： Gregory Snider ,  Philip Kuekes ,  Duncan Stewart

    发明人： Gregory Snider ,  Philip Kuekes ,  Duncan Stewart

    IPC分类号： H03K19/173

    CPC分类号： B82Y10/00 ,  G06N99/007 ,  H01L27/101

    摘要： One embodiment of the present invention is an array of nanoscale latches interconnected by a nanowire bus to form a latch array. Each nanoscale latch in the nanoscale-latch array serves as a nanoscale register, and is driven by a nanoscale control line. Primitive operations for the latch array can be defined as sequences of one or more inputs to one or more of the nanowire data bus and nanoscale control lines. In various latch-array embodiments of the present invention, information can be transferred from one nanoscale latch to another nanoscale latch in a controlled fashion, and sequences of information-transfer operations can be devised to implement arbitrary Boolean logic operations and operators, including NOT, AND, OR, XOR, NOR, NAND, and other such Boolean logic operators and operations, as well as input and output functions. Nanoscale-latch arrays can be combined and interconnected in an almost limitless number of different ways to construct arbitrarily complex, sequential, parallel, or both parallel and sequential computing engines that represent additional embodiments of the present invention.

    摘要翻译： 本发明的一个实施例是通过纳米线总线互连以形成锁存阵列的纳米级锁存器的阵列。 纳米尺度锁存阵列中的每个纳米级锁存器用作纳米尺度寄存器，并由纳米尺度控制线驱动。 锁存阵列的原始操作可以被定义为一个或多个输入到纳米线数据总线和纳米尺度控制线中的一个或多个的序列。 在本发明的各种锁存阵列实施例中，可以以受控的方式将信息从一个纳米级锁存器传送到另一个纳米级锁存器，并且可以设计信息传送操作的序列以实现任意的布尔逻辑运算，并且运算符包括NOT， AND，OR，XOR，NOR，NAND和其他这样的布尔逻辑运算符和操作，以及输入和输出功能。 纳秒级锁存器阵列可以以几乎无限数量的不同方式组合和互连，以构造代表本发明附加实施例的任意复杂，顺序，并行或并行和顺序的计算引擎。

    TUNNELING-RESISTOR-JUNCTION-BASED MICROSCALE/NANOSCALE DEMULTIPLEXER ARRAYS
    3.
    发明申请
    TUNNELING-RESISTOR-JUNCTION-BASED MICROSCALE/NANOSCALE DEMULTIPLEXER ARRAYS 失效
    基于隧道式电阻器的微阵列/纳米解复用器阵列

    公开(公告)号：US20070176801A1

    公开(公告)日：2007-08-02

    申请号：US11343325

    申请日：2006-01-30

    申请人： Warren Robinett ,  Gregory Snider ,  Duncan Stewart ,  Joseph Straznicky

    发明人： Warren Robinett ,  Gregory Snider ,  Duncan Stewart ,  Joseph Straznicky

    IPC分类号： H03M7/00

    CPC分类号： G11C8/10 ,  G11C13/0023 ,  H03M13/51

    摘要： Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodiment of the present invention, an encoder-demultiplexer comprises a number of input signal lines and an encoder that generates an n-bit-constant-weight-code code-word internal address for each different input address received on the input signal lines. The encoder-demultiplexer includes n microscale signal lines on which an n-bit-constant-weight-code code-word internal address is output by the encoder, where each microscale signal line carries one bit of the n-bit-constant-weight-code code-word internal address. The encoder-demultiplexer also includes a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with the n microscale signal lines via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal address.

    摘要翻译： 本发明的各种实施例涉及包括隧穿电阻器纳米线结的解复用器，以及纳米线寻址方法，用于在纳米尺度和混合尺度解复用器中可靠地寻址纳米线信号线。 在本发明的一个实施例中，编码器 - 解复用器包括多个输入信号线和一个编码器，其生成在输入信号线上接收的每个不同输入地址的n位恒权重码码字内部地址 。 编码器 - 解复用器包括n个微米级信号线，编码器输出n位恒定权重码码字内部地址，其中每个微信号线承载n位恒权重码内部地址的一位， 代码字内部地址。 编码器 - 解复用器还包括通过隧道电阻器结与n个微米级信号线互连的多个编码器 - 解复用器寻址的纳米线信号线，编码器 - 解复用器寻址的纳米线信号线每个与n比特恒权重信号线相关联， 代码字内部地址。

    Switching device and methods for controlling electron tunneling therein
    5.
    发明申请
    Switching device and methods for controlling electron tunneling therein 有权
    用于控制电子隧穿的开关装置和方法

    公开(公告)号：US20070252128A1

    公开(公告)日：2007-11-01

    申请号：US11414578

    申请日：2006-04-28

    申请人： R. Williams ,  Zhiyong Li ,  Douglas Ohlberg ,  Philip Kuekes ,  Duncan Stewart

    发明人： R. Williams ,  Zhiyong Li ,  Douglas Ohlberg ,  Philip Kuekes ,  Duncan Stewart

    IPC分类号： H01L29/02 ,  H01L47/00

    CPC分类号： G11C13/02 ,  G11C13/0009 ,  G11C2213/77 ,  H01L51/0591

    摘要： A switching device includes at least one bottom electrode and at least one top electrode. The top electrode crosses the bottom electrode at a non-zero angle, thereby forming a junction. A metal oxide layer is established on at least one of the bottom electrode or the top electrode. A molecular layer including a monolayer of organic molecules and a source of water molecules is established in the junction. Upon introduction of a forward bias, the molecular layer facilitates a redox reaction between the electrodes, thereby reducing a tunneling gap between the electrodes.

    摘要翻译： 开关装置包括至少一个底部电极和至少一个顶部电极。 顶部电极以非零角度穿过底部电极，从而形成结。 在底电极或顶电极中的至少一个上建立金属氧化物层。 在连接处建立了包括有机分子单层和水分子源的分子层。 在引入正向偏压时，分子层促进电极之间的氧化还原反应，从而减少电极之间的隧道间隙。

    Active interconnects and control points in integrated circuits
    8.
    发明申请
    Active interconnects and control points in integrated circuits 有权
    集成电路中的有源互连和控制点

    公开(公告)号：US20060238217A1

    公开(公告)日：2006-10-26

    申请号：US11112795

    申请日：2005-04-21

    申请人： R. Williams ,  Philip Kuekes ,  Frederick Perner ,  Greg Snider ,  Duncan Stewart

    发明人： R. Williams ,  Philip Kuekes ,  Frederick Perner ,  Greg Snider ,  Duncan Stewart

    IPC分类号： H03K19/003

    CPC分类号： H05K7/1092 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In various embodiments of the present invention, tunable resistors are introduced at the interconnect layer of integrated circuits in order to provide a means for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronic characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains. In some cases, components and modules may be turned off, while, in other cases, components and modules may be turned on.

    摘要翻译： 在本发明的各种实施例中，在集成电路的互连层处引入可调电阻器，以便提供用于调整集成电路内的内部电压和/或电流水平以修复有缺陷的部件或者在制造后配置集成电路的装置 。 例如，当诸如晶体管的某些内部组件由于制造缺陷而没有指定的电子特性时，可以使用根据本发明的实施例的包括在集成电路的互连层中的可调电阻器的可变电阻的调整 以调整内部电压和/或电平以便改善有缺陷的部件。 在其他情况下，可调谐电阻器可以用作开关以配置集成电路部件，包括单独的晶体管和逻辑门以及更大的分层结构的功能模块和域。 在某些情况下，可能会关闭组件和模块，而在其他情况下，可能会打开组件和模块。