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    Memory components and controllers that calibrate multiphase synchronous timing references
    2.
    发明授权
    Memory components and controllers that calibrate multiphase synchronous timing references 有权

    公开(公告)号：US11289139B2

    公开(公告)日：2022-03-29

    申请号：US16793638

    申请日：2020-02-18

    Applicant: Rambus Inc.

    Inventor： Thomas Giovannini ,  Scott C. Best ,  Lei Luo ,  Ian Shaeffer

    IPC: G06F12/00 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  G11C29/56

    Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

    Memory components and controllers that calibrate multiphase synchronous timing references
    3.
    发明授权
    Memory components and controllers that calibrate multiphase synchronous timing references 有权

    公开(公告)号：US09824730B2

    公开(公告)日：2017-11-21

    申请号：US15228644

    申请日：2016-08-04

    Applicant: Rambus Inc.

    Inventor： Thomas Giovannini ,  Scott C Best ,  Lei Luo ,  Ian Shaeffer

    IPC: G06F12/00 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  G11C29/56

    CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

    Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

    Memory system design using buffer(s) on a mother board
    6.
    发明授权
    Memory system design using buffer(s) on a mother board 有权

    公开(公告)号：US11003601B2

    公开(公告)日：2021-05-11

    申请号：US16837844

    申请日：2020-04-01

    Applicant: Rambus Inc.

    Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

    IPC: G06F13/20 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

    Methods and systems for recovering intermittent timing-reference signals
    7.
    发明授权
    Methods and systems for recovering intermittent timing-reference signals 有权
    用于恢复间歇定时参考信号的方法和系统

    公开(公告)号：US09389637B2

    公开(公告)日：2016-07-12

    申请号：US13867954

    申请日：2013-04-22

    Applicant: Rambus Inc.

    Inventor： Huy Nguyen ,  Vijay Gadde ,  Kambiz Kaviani ,  Thomas Giovannini ,  Todd Bystrom

    IPC: G06F1/12

    CPC classification number: G06F1/12

    Abstract: A source-synchronous communication system in which a first integrated circuit (IC) conveys a data signal and concomitant strobe signal to a second IC. One or both ICs support hysteresis for the strobe channel that allows the second IC to distinguish between strobe preambles and noise, and thus prevent the false triggering of data capture. Hysteresis may also be employed to quickly settle the strobe channel to an inactive level after receipt of a strobe postamble.

    Abstract translation: 一种源同步通信系统，其中第一集成电路（IC）向第二IC传送数据信号和伴随选通信号。 一个或两个IC支持选通通道的滞后，允许第二IC区分选通前导和噪声，从而防止数据捕获的错误触发。 还可以采用迟滞来在接收到选通后同步码之后快速地将频闪通道置于非活动状态。

    Memory system design using buffer(s) on a mother board
    9.
    发明授权
    Memory system design using buffer(s) on a mother board 有权

    公开(公告)号：US10169258B2

    公开(公告)日：2019-01-01

    申请号：US15071072

    申请日：2016-03-15

    Applicant: Rambus Inc.

    Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

    IPC: G06F13/20 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

    MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES
    10.
    发明申请
    MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES 审中-公开

    公开(公告)号：US20180137902A1

    公开(公告)日：2018-05-17

    申请号：US15794177

    申请日：2017-10-26

    Applicant: Rambus Inc.

    Inventor： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

    IPC: G11C7/22 ,  G11C29/56 ,  G11C29/50 ,  G11C29/02

    CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

    Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

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