公开(公告)号：US20210336039A1

公开(公告)日：2021-10-28

申请号：US17190891

申请日：2021-03-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi YOSHITOMI

IPC: H01L29/66 ,  H01L27/1157

Abstract: Reliability and performance of a semiconductor device are improved. First, a first mask pattern is formed on the semiconductor substrate in each of first to third regions. Next, a second mask pattern made of a material that is different from a material configuring the first mask pattern is formed on a side surface of the first mask pattern and on the semiconductor substrate in each of the first to third regions. Next, by an anisotropic etching process performed to the semiconductor substrate, a plurality of fins protruding from the recessed upper surface of the semiconductor substrate are formed. In the manner, fins each having a different structure from that of a fin in the first region can be formed in the second and third regions.

公开(公告)号：US20180061997A1

公开(公告)日：2018-03-01

申请号：US15626092

申请日：2017-06-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Masao INOUE ,  Atsushi YOSHITOMI

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/785

Abstract: A memory cell includes a control gate electrode and a memory gate electrode. The control gate electrode is formed over the upper surface and the sidewall of a fin FA including apart of a semiconductor substrate. The memory gate electrode is formed over one side surface of the control gate electrode and the upper surface and the sidewall of the fin through an ONO film, in a position adjacent to the one side surface of the control gate electrode. Further, the control gate electrode and the memory gate electrode are formed of n-type polycrystalline silicon. A first metal film is provided between the gate electrode and the control gate electrode. A second metal film is provided between the ONO film and the memory gate electrode. A work function of the first metal film is greater than a work function of the second metal film.

公开(公告)号：US20190035800A1

公开(公告)日：2019-01-31

申请号：US16020094

申请日：2018-06-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA ,  Atsushi YOSHITOMI

IPC: H01L27/11573 ,  H01L27/11568

CPC classification number: H01L27/11573 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/4234

Abstract: To provide a semiconductor device capable of having an ONO-film-configuring second oxide film with an optimized thickness. The semiconductor device has a semiconductor substrate having a first surface, a first gate insulating film placed on the first surface located in a first transistor formation region, and a second gate insulating film placed on the first surface located in a second transistor formation region. The first gate insulating film has a first oxide film, a first nitride film placed thereon, and a second oxide film placed thereon. The second oxide film includes a first layer and a second layer placed thereon. The height of the first surface in a region where the second insulating film is placed is lower than that in a region where the first gate insulating film is placed. The nitrogen concentration in the first layer is higher than that in the second layer.

公开(公告)号：US20180374924A1

公开(公告)日：2018-12-27

申请号：US15978296

申请日：2018-05-14

Applicant: Renesas Electronics Corporation

Inventor： Atsushi YOSHITOMI ,  Yoshiyuki KAWASHIMA

IPC: H01L29/423 ,  H01L27/11568 ,  H01L29/66 ,  H01L29/792 ,  H01L29/78

CPC classification number: H01L29/4234 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42372 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/792

Abstract: To provide a semiconductor device having improved reliability by relaxing the unevenness of the injection distribution of electrons and holes into a charge accumulation film attributable to the shape of the fin of a MONOS memory comprised of a fin transistor. Of a memory gate electrode configuring a memory cell formed above a fin, a portion contiguous to an ONO film that covers the upper surface of the fin and a portion contiguous to the ONO film that covers the side surface of the fin are made of electrode materials different in work function, respectively, and the boundary surface between them is located below the upper surface of the fin.

公开(公告)号：US20180076206A1

公开(公告)日：2018-03-15

申请号：US15699756

申请日：2017-09-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi YOSHITOMI ,  Yoshiyuki KAWASHIMA

IPC: H01L27/1157 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L29/408 ,  H01L29/42344 ,  H01L29/4983 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/792

Abstract: The reliability and performances of a semiconductor device having a nonvolatile memory are improved. A control gate electrode is formed over a semiconductor substrate via a first insulation film. A memory gate electrode is formed over the semiconductor substrate via a second insulation film having a charge accumulation part. The second insulation film is formed across between the semiconductor substrate and the memory gate electrode, and between the control gate electrode and the memory gate electrode. Between the control gate electrode and the memory gate electrode, a third insulation film is formed between the second insulation film and the memory gate electrode. The third insulation film is not formed under the memory gate electrode. A part of the memory gate electrode is present under the lower end face of the third insulation film.