公开(公告)号：US20220157964A1

公开(公告)日：2022-05-19

申请号：US17513404

申请日：2021-10-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA ,  Masao INOUE

IPC: H01L29/51 ,  H01L29/792 ,  H01L29/423

Abstract: A memory cell which is a non-volatile memory cell includes a gate insulating film having a charge storage layer capable of retaining charge and a memory gate electrode formed on the gate insulating film. The charge storage layer includes a first insulating film containing hafnium and silicon and a second insulating film formed on the first insulating film and containing hafnium and silicon. Here, a hafnium concentration of the first insulating film is lower than a hafnium concentration of the second insulating film, and a bandgap of the first insulating film is larger than a bandgap of the second insulating film.

公开(公告)号：US20130341727A1

公开(公告)日：2013-12-26

申请号：US13945282

申请日：2013-07-18

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro SHIMAMOTO ,  Jiro YUGAMI ,  Masao INOUE ,  Masaharu MIZUTANI

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/28035 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

Abstract: Disclosed is a semiconductor device including a first MISFET of an n channel type and a second MISFET of a p channel type, each of the MISFETs being configured with a gate insulating film featuring a silicon oxide film or a silicon oxynitride film and a gate electrode including a conductive silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film in both the first and second MISFETs such that metal atoms with a surface density of 1×1013 to 5×1014 atoms/cm2 are contained near the interface and each of the first and second MISFETs having a channel region containing an impurity the concentration of which is equal to or lower than 1.2×1018/cm3.

Abstract translation: 公开了一种包括n沟道型的第一MISFET和ap沟道型的第二MISFET的半导体器件，每个MISFET被配置有具有硅氧化膜或氮氧化硅膜的栅极绝缘膜和包括 位于栅极绝缘膜上的导电硅膜。 金属元素如Hf在第一和第二MISFET中的栅电极和栅极绝缘膜之间的界面附近引入，使得表面密度为1×1013至5×1014原子/ cm2的金属原子包含在界面附近 并且第一和第二MISFET中的每一个具有含有浓度等于或低于1.2×1018 / cm3的杂质的沟道区。

公开(公告)号：US20200027996A1

公开(公告)日：2020-01-23

申请号：US16452261

申请日：2019-06-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masao INOUE ,  Masaru KADOSHIMA ,  Yoshiyuki KAWASHIMA ,  Ichiro YAMAKAWA

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

Abstract: A memory cell, which is a nonvolatile memory cell, includes a gate dielectric film having charge storage layer capable of holding charges, and a memory gate electrode formed on the gate dielectric film. The charge storage layer includes an insulating film containing hafnium, silicon, and oxygen, an insertion layer formed on the insulating film and containing aluminum, and an insulating film formed on the insertion layer and containing hafnium, silicon, and oxygen.

公开(公告)号：US20200251599A1

公开(公告)日：2020-08-06

申请号：US16857986

申请日：2020-04-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masao INOUE

IPC: H01L29/792 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

Abstract: The performances of a semiconductor device of a memory element are improved. Over a semiconductor substrate, a gate electrode for memory element is formed via overall insulation film of gate insulation film for memory element. The overall insulation film has first insulation film, second insulation film over first insulation film, third insulation film over second insulation film, fourth insulation film over third insulation film, and fifth insulation film over fourth insulation film. The second insulation film is an insulation film having charge accumulation function. Each band gap of first insulation film and third insulation film is larger than the band gap of second insulation film. The third insulation film is polycrystal film including high dielectric constant material containing metallic element and oxygen. Fifth insulation film is polycrystal film including the same material as that for third insulation film. Fourth insulation film includes different material from that for third insulation film.

公开(公告)号：US20190148562A1

公开(公告)日：2019-05-16

申请号：US16126784

申请日：2018-09-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masao INOUE

IPC: H01L29/792 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11568

Abstract: The performances of a semiconductor device of a memory element are improved. Over a semiconductor substrate, a gate electrode for memory element is formed via overall insulation film of gate insulation film for memory element. The overall insulation film has first insulation film, second insulation film over first insulation film, third insulation film over second insulation film, fourth insulation film over third insulation film, and fifth insulation film over fourth insulation film. The second insulation film is an insulation film having charge accumulation function. Each band gap of first insulation film and third insulation film is larger than the band gap of second insulation film. The third insulation film is polycrystal film including high dielectric constant material containing metallic element and oxygen. Fifth insulation film is polycrystal film including the same material as that for third insulation film. Fourth insulation film includes different material from that for third insulation film.

公开(公告)号：US20180308991A1

公开(公告)日：2018-10-25

申请号：US15904601

申请日：2018-02-26

Applicant: Renesas Electronics Corporation

Inventor： Masaru KADOSHIMA ,  Masao INOUE

IPC: H01L29/792 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11568

CPC classification number: H01L29/7923 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66833

Abstract: To improve the performance of a semiconductor device, the semiconductor device includes an insulating film portion over a semiconductor substrate. The insulating film portion includes an insulating film containing silicon and oxygen, a first charge storage film containing silicon and nitrogen, an insulating film containing silicon and oxygen, a second charge storage film containing silicon and nitrogen, and an insulating film containing silicon and oxygen. The first charge storage film is included by two charge storage films.

公开(公告)号：US20180061997A1

公开(公告)日：2018-03-01

申请号：US15626092

申请日：2017-06-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Masao INOUE ,  Atsushi YOSHITOMI

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/785

Abstract: A memory cell includes a control gate electrode and a memory gate electrode. The control gate electrode is formed over the upper surface and the sidewall of a fin FA including apart of a semiconductor substrate. The memory gate electrode is formed over one side surface of the control gate electrode and the upper surface and the sidewall of the fin through an ONO film, in a position adjacent to the one side surface of the control gate electrode. Further, the control gate electrode and the memory gate electrode are formed of n-type polycrystalline silicon. A first metal film is provided between the gate electrode and the control gate electrode. A second metal film is provided between the ONO film and the memory gate electrode. A work function of the first metal film is greater than a work function of the second metal film.

公开(公告)号：US20140312406A1

公开(公告)日：2014-10-23

申请号：US14173074

申请日：2014-02-05

Applicant: Renesas Electronics Corporation

Inventor： Masao INOUE ,  Yoshiki MARUYAMA ,  Akio NISHIDA ,  Yorinobu KUNIMUNE ,  Kota FUNAYAMA

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/4925 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/28035 ,  H01L21/28176 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66825

Abstract: To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film (21) on a substrate (10); forming an interlayer oxide layer (22) on a surface of the first polysilicon film (21); forming a second polysilicon film (23) in contact with the interlayer oxide layer (22) above the first polysilicon film (21); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film (23).

Abstract translation: 为了控制层叠多晶硅膜上的晶粒生长，提供了制造半导体器件的方法。 该方法包括：在衬底（10）上形成第一多晶硅膜（21）; 在所述第一多晶硅膜（21）的表面上形成层间氧化物层（22）; 形成与第一多晶硅膜（21）上方的层间氧化物层（22）接触的第二多晶硅膜（23）。 在形成第二多晶硅膜（23）之后，在含氮气体气氛中，在高于第一和第二多晶硅膜的成膜温度的温度下进行退火。