公开(公告)号：US20130112852A1

公开(公告)日：2013-05-09

申请号：US13661724

申请日：2012-10-26

Applicant: Renesas Electronics Corporation

Inventor： Shunsuke KIZUNA ,  Katsumi DOSAKA ,  Hiroto UTSUNOMIYA

IPC: H04N5/378

CPC classification number: H04N5/378

Abstract: A solid-state image pickup device includes a column ADC realizing higher precision and higher-speed conversion. Converters converts a signal of each pixels output via a corresponding vertical read line to a digital value by sequentially executing first to N-th (N: integer of three or larger) conversion stages. In the first to (N−1)th conversion stages, each converter determines a value of upper bits including the most significant bit of a digital value by comparing the voltage at a retention stage with a reference voltage while changing the voltage at a retention node. In the N-th conversion stage, each converter determines a value of remaining bits to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N−1)th conversion stage or a range exceeding the range.

Abstract translation: 固态图像拾取装置包括实现更高精度和更高速度转换的列ADC。 转换器通过顺序地执行第一至第N（三个或三个以上的整数）转换级，将通过相应垂直读取线的每个像素输出的信号转换为数字值。 在第一到第（N-1）个转换级中，每个转换器通过将保持级的电压与参考电压进行比较来确定包括数字值的最高有效位的高位数值，同时改变保持节点处的电压 。 在第N次转换阶段，每个转换器通过将保持节点处的电压与参考电压进行比较来确定剩余比特到最低有效位的值，同时在保持节点的电压步长范围内连续改变电压 （N-1）转换级或超出范围的范围。

公开(公告)号：US20160212367A1

公开(公告)日：2016-07-21

申请号：US15082913

申请日：2016-03-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroto UTSUNOMIYA ,  Katsumi DOSAKA ,  Hiroshi KATO ,  Fukashi MORISHITA ,  Fumiyasu SASAKI

IPC: H04N5/3745 ,  H04N5/376 ,  H03M1/66 ,  H04N5/378

CPC classification number: H04N5/37455 ,  H03M1/1205 ,  H03M1/144 ,  H03M1/403 ,  H03M1/66 ,  H03M2201/16 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3765 ,  H04N5/378

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。

公开(公告)号：US20150288904A1

公开(公告)日：2015-10-08

申请号：US14746030

申请日：2015-06-22

Applicant: Renesas Electronics Corporation

Inventor： SHUNSUKE KIZUNA ,  Katsumi DOSAKA ,  Hiroto UTSUNOMIYA

IPC: H04N5/378

CPC classification number: H04N5/378

Abstract: A solid-state image pickup device includes a column ADC realizing higher precision and higher-speed conversion. Converters converts a signal of each pixels output via a corresponding vertical read line to a digital value by sequentially executing first to N-th (N: integer of three or larger) conversion stages. In the first to (N−1)th conversion stages, each converter determines a value of upper bits including the most significant bit of a digital value by comparing the voltage at a retention stage with a reference voltage while changing the voltage at a retention node. In the N-th conversion stage, each converter determines a value of remaining bits to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N−1)th conversion stage or a range exceeding the range.

Abstract translation: 固态图像拾取器件包括实现更高精度和更高速度转换的列ADC。 转换器通过顺序地执行第一至第N（三个或三个以上的整数）转换级，将通过相应垂直读取线的每个像素输出的信号转换为数字值。 在第一到第（N-1）个转换级中，每个转换器通过将保持级的电压与参考电压进行比较来确定包括数字值的最高有效位的高位数值，同时改变保持节点处的电压 。 在第N次转换阶段，每个转换器通过将保持节点处的电压与参考电压进行比较来确定剩余比特到最低有效位的值，同时在保持节点的电压步长范围内连续改变电压 （N-1）转换级或超出范围的范围。

公开(公告)号：US20140226049A1

公开(公告)日：2014-08-14

申请号：US14256680

申请日：2014-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroto UTSUNOMIYA ,  Katsumi DOSAKA ,  Hiroshi KATO ,  Fukashi MORISHITA ,  Fumiyasu SASAKI

IPC: H04N5/369

CPC classification number: H04N5/37455 ,  H03M1/1205 ,  H03M1/144 ,  H03M1/403 ,  H03M1/66 ,  H03M2201/16 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3765 ,  H04N5/378

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。