公开(公告)号：US20160212367A1

公开(公告)日：2016-07-21

申请号：US15082913

申请日：2016-03-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroto UTSUNOMIYA ,  Katsumi DOSAKA ,  Hiroshi KATO ,  Fukashi MORISHITA ,  Fumiyasu SASAKI

IPC: H04N5/3745 ,  H04N5/376 ,  H03M1/66 ,  H04N5/378

CPC classification number: H04N5/37455 ,  H03M1/1205 ,  H03M1/144 ,  H03M1/403 ,  H03M1/66 ,  H03M2201/16 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3765 ,  H04N5/378

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。

公开(公告)号：US20150115135A1

公开(公告)日：2015-04-30

申请号：US14588787

申请日：2015-01-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunsuke OKURA ,  Koji SHIDA ,  Hiroshi KATO

IPC: H04N5/378

CPC classification number: H04N5/378 ,  H03M1/00

Abstract: There is a need to provide a solid-state imaging apparatus capable of highly accurately analog-to-digital converting an analog voltage output from a pixel circuit. The solid-state imaging apparatus supplies a counter code to an integral A/D converter. The counter code CD includes 3-phase clock signals and gray signals. The clock signals each have a cycle equal to specified cycle multiplied by 8 and allow phases to shift from each other by specified cycle. The gray signals linearly increase count values at a cycle equal to specified cycle multiplied by 4. The counter code reverses only the logical level of a signal when a count value changes. A count value error can be limited to a minimum.

Abstract translation: 需要提供能够高精度地模数转换从像素电路输出的模拟电压的固态成像装置。 固态成像装置向积分A / D转换器提供计数器代码。 计数器代码CD包括三相时钟信号和灰度信号。 时钟信号各自具有等于指定周期的周期乘以8，并允许相位相互指定周期相移。 灰度信号在等于指定周期的周期乘以4的线性增加计数值。当计数值改变时，计数器代码仅反转信号的逻辑电平。 计数值错误可以限制在最小值。

公开(公告)号：US20140226049A1

公开(公告)日：2014-08-14

申请号：US14256680

申请日：2014-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroto UTSUNOMIYA ,  Katsumi DOSAKA ,  Hiroshi KATO ,  Fukashi MORISHITA ,  Fumiyasu SASAKI

IPC: H04N5/369

CPC classification number: H04N5/37455 ,  H03M1/1205 ,  H03M1/144 ,  H03M1/403 ,  H03M1/66 ,  H03M2201/16 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3765 ,  H04N5/378

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。

公开(公告)号：US20130284888A1

公开(公告)日：2013-10-31

申请号：US13870893

申请日：2013-04-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunsuke OKURA ,  Koji SHIDA ,  Hiroshi KATO

IPC: H04N5/378

CPC classification number: H04N5/378 ,  H03M1/00

Abstract: There is a need to provide a solid-state imaging apparatus capable of highly accurately analog-to-digital converting an analog voltage output from a pixel circuit. The solid-state imaging apparatus supplies a counter code to an integral A/D converter. The counter code CD includes 3-phase clock signals and gray signals. The clock signals each have a cycle equal to specified cycle multiplied by 8 and allow phases to shift from each other by specified cycle. The gray signals linearly increase count values at a cycle equal to specified cycle multiplied by 4. The counter code reverses only the logical level of a signal when a count value changes. A count value error can be limited to a minimum.