公开(公告)号：US09559644B2

公开(公告)日：2017-01-31

申请号：US14931448

申请日：2015-11-03

Applicant: RF Micro Devices, Inc.

Inventor： George Maxim ,  Dirk Robert Walter Leipold ,  Baker Scott ,  Ralph Christopher Nieri

IPC: H03F3/04 ,  H03F3/193 ,  H03F1/26 ,  H04B1/10 ,  H04B7/08 ,  H04W72/04 ,  H03F1/02 ,  H03F1/22

CPC classification number: H03F3/193 ,  H03F1/0261 ,  H03F1/223 ,  H03F1/26 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H04B1/1036 ,  H04B7/08 ,  H04B2001/1063 ,  H04W72/04

Abstract: Circuitry includes a floating-body main field-effect transistor (FET) device, a body-contacted cascode FET device, and biasing circuitry coupled to the floating-body main FET device and the body-contacted cascode FET device. The floating-body main FET device includes a gate contact, a drain contact, and a source contact. The body-contacted cascode FET device includes a gate contact, a drain contact coupled to a supply voltage, and a source contact coupled to the drain contact of the floating-body main FET device and to a body region of the body-contacted cascode FET device. The biasing circuitry is coupled to the gate contact of the floating-body main FET device and the gate contact of the body-contacted cascode FET device and configured to provide biasing signals to the floating-body main FET device and the body-contacted cascode FET device such that a majority of the supply voltage is provided across the body-contacted cascode FET device.

Abstract translation: 电路包括浮体主场效应晶体管（FET）器件，体接触共源共栅FET器件和耦合到浮体主FET器件和体接触共源共栅FET器件的偏置电路。 浮体主FET器件包括栅极接触，漏极接触和源极接触。 身体接触的共源共栅型FET器件包括栅极接触，耦合到电源电压的漏极接触以及耦合到浮体主FET器件的漏极接触和与身体接触的共源共栅FET的体区的源极接触 设备。 偏置电路耦合到浮体主FET器件的栅极接触和体接触共源共栅FET器件的栅极接触，并且被配置为向浮体主FET器件和体接触的共源共栅FET提供偏置信号 器件，使得大部分电源电压被提供在身体接触的共源共栅型FET器件上。

公开(公告)号：US20140347121A1

公开(公告)日：2014-11-27

申请号：US14455346

申请日：2014-08-08

Applicant: RF Micro Devices, Inc.

Inventor： Nathaniel Peachey ,  Ralph Christopher Nieri

IPC: G05F3/20

CPC classification number: G05F3/205 ,  G05F3/16

Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.

公开(公告)号：US08829981B2

公开(公告)日：2014-09-09

申请号：US13889583

申请日：2013-05-08

Applicant: RF Micro Devices, Inc.

Inventor： Nathaniel Peachey ,  Ralph Christopher Nieri

IPC: G05F1/10 ,  G05F3/02

CPC classification number: G05F3/205 ,  G05F3/16

Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.

Abstract translation: 自偏压晶体管开关电路包括主晶体管，偏置晶体管，第一电容器和第二电容器。 主晶体管的主体通过绝缘层与主晶体管的栅极，漏极和源极隔离。 第一电容器耦合在主晶体管的源极和栅极之间。 第二电容器耦合在主晶体管的源极和主体之间。 主晶体管的主体和漏极耦合在一起。 偏置晶体管的栅极和漏极耦合到主晶体管的栅极。 偏置晶体管的漏极耦合到主晶体管的漏极。 自偏置晶体管开关电路适于在主晶体管的漏极处接收振荡信号，并且使用振荡信号来适当地偏置主晶体管。

公开(公告)号：US20140091858A1

公开(公告)日：2014-04-03

申请号：US13889583

申请日：2013-05-08

Applicant: RF MICRO DEVICES, INC.

Inventor： Nathaniel Peachey ,  Ralph Christopher Nieri

IPC: G05F3/16

CPC classification number: G05F3/205 ,  G05F3/16

Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.

Abstract translation: 自偏压晶体管开关电路包括主晶体管，偏置晶体管，第一电容器和第二电容器。 主晶体管的主体通过绝缘层与主晶体管的栅极，漏极和源极隔离。 第一电容器耦合在主晶体管的源极和栅极之间。 第二电容器耦合在主晶体管的源极和主体之间。 主晶体管的主体和漏极耦合在一起。 偏置晶体管的栅极和漏极耦合到主晶体管的栅极。 偏置晶体管的漏极耦合到主晶体管的漏极。 自偏置晶体管开关电路适于在主晶体管的漏极处接收振荡信号，并且使用振荡信号来适当地偏置主晶体管。

公开(公告)号：US20160126906A1

公开(公告)日：2016-05-05

申请号：US14931448

申请日：2015-11-03

Applicant: RF Micro Devices, Inc.

Inventor： George Maxim ,  Dirk Robert Walter Leipold ,  Baker Scott ,  Ralph Christopher Nieri

IPC: H03F3/193 ,  H03F1/26 ,  H03F1/02

CPC classification number: H03F3/193 ,  H03F1/0261 ,  H03F1/223 ,  H03F1/26 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H04B1/1036 ,  H04B7/08 ,  H04B2001/1063 ,  H04W72/04

Abstract: Circuitry includes a floating-body main field-effect transistor (FET) device, a body-contacted cascode FET device, and biasing circuitry coupled to the floating-body main FET device and the body-contacted cascode FET device. The floating-body main FET device includes a gate contact, a drain contact, and a source contact. The body-contacted cascode FET device includes a gate contact, a drain contact coupled to a supply voltage, and a source contact coupled to the drain contact of the floating-body main FET device and to a body region of the body-contacted cascode FET device. The biasing circuitry is coupled to the gate contact of the floating-body main FET device and the gate contact of the body-contacted cascode FET device and configured to provide biasing signals to the floating-body main FET device and the body-contacted cascode FET device such that a majority of the supply voltage is provided across the body-contacted cascode FET device.

Abstract translation: 电路包括浮体主场效应晶体管（FET）器件，体接触共源共栅FET器件和耦合到浮体主FET器件和体接触共源共栅FET器件的偏置电路。 浮体主FET器件包括栅极接触，漏极接触和源极接触。 身体接触的共源共栅型FET器件包括栅极接触，耦合到电源电压的漏极接触以及耦合到浮体主FET器件的漏极接触和与身体接触的共源共栅FET的体区的源极接触 设备。 偏置电路耦合到浮体主FET器件的栅极接触和体接触共源共栅FET器件的栅极接触，并且被配置为向浮体主FET器件和体接触的共源共栅FET提供偏置信号 器件，使得大部分电源电压被提供在身体接触的共源共栅型FET器件上。

公开(公告)号：US09244478B2

公开(公告)日：2016-01-26

申请号：US14455346

申请日：2014-08-08

Applicant: RF Micro Devices, Inc.

Inventor： Nathaniel Peachey ,  Ralph Christopher Nieri

IPC: G05F3/16 ,  G05F3/20

CPC classification number: G05F3/205 ,  G05F3/16

Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.

Abstract translation: 自偏压晶体管开关电路包括主晶体管，偏置晶体管，第一电容器和第二电容器。 主晶体管的主体通过绝缘层与主晶体管的栅极，漏极和源极隔离。 第一电容器耦合在主晶体管的源极和栅极之间。 第二电容器耦合在主晶体管的源极和主体之间。 主晶体管的主体和漏极耦合在一起。 偏置晶体管的栅极和漏极耦合到主晶体管的栅极。 偏置晶体管的漏极耦合到主晶体管的漏极。 自偏置晶体管开关电路适于在主晶体管的漏极处接收振荡信号，并且使用振荡信号来适当地偏置主晶体管。