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公开(公告)号：US08824217B2
公开(公告)日：2014-09-02
申请号：US13929950
申请日：2013-06-28
Applicant: RF Micro Devices, Inc.
Inventor： Nathaniel Peachey , Joseph Hubert Colles , Jeffrey D. Potts
CPC classification number: G11C7/12 , G11C5/02 , G11C5/06 , G11C5/147 , G11C7/02 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C13/04 , H01L23/60 , H01L2924/0002 , H02H9/041 , H01L2924/00
Abstract: The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.
Abstract translation: 所描述的装置，系统和方法包括具有闩锁的静电放电夹具，以防止电抗放电保护电路响应于电源轨的波动而错误触发。
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公开(公告)号：US09997509B2
公开(公告)日：2018-06-12
申请号：US14687310
申请日：2015-04-15
Applicant: RF Micro Devices, Inc.
Inventor： Muhammad Iqbal Chaudhry , Nathaniel Peachey
CPC classification number: H01L27/0251 , H01L27/0259
Abstract: Aspects disclosed in the detailed description include an electrostatic discharge (ESD) protection circuit. In this regard, in one aspect, an ESD protection circuit is provided to protect an integrated circuit (IC) during fabrication and production. An ESD detection circuitry detects an ESD event by detecting a voltage spike between a supply rail and a ground rail exceeding an ESD threshold voltage. In response to detecting the ESD event, an ESD clamping circuitry is activated to discharge the ESD event, thus protecting the IC from being damaged by the ESD event. By detecting the ESD event based on the ESD threshold voltage, as opposed to detecting the ESD event based on rise time of the voltage spike, it is possible to prevent the ESD clamping circuitry from missing voltage spikes associated with a slow rise time or being falsely activated by a normal power-on voltage associated with a fast rise time.
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公开(公告)号：US20150325568A1
公开(公告)日：2015-11-12
申请号：US14687310
申请日：2015-04-15
Applicant: RF Micro Devices, Inc.
Inventor： Muhammad Iqbal Chaudhry , Nathaniel Peachey
IPC: H01L27/02
CPC classification number: H01L27/0251 , H01L27/0259
Abstract: Aspects disclosed in the detailed description include an electrostatic discharge (ESD) protection circuit. In this regard, in one aspect, an ESD protection circuit is provided to protect an integrated circuit (IC) during fabrication and production. An ESD detection circuitry detects an ESD event by detecting a voltage spike between a supply rail and a ground rail exceeding an ESD threshold voltage. In response to detecting the ESD event, an ESD clamping circuitry is activated to discharge the ESD event, thus protecting the IC from being damaged by the ESD event. By detecting the ESD event based on the ESD threshold voltage, as opposed to detecting the ESD event based on rise time of the voltage spike, it is possible to prevent the ESD clamping circuitry from missing voltage spikes associated with a slow rise time or being falsely activated by a normal power-on voltage associated with a fast rise time.
Abstract translation: 在详细描述中公开的方面包括静电放电（ESD）保护电路。 在这方面，在一个方面，提供ESD保护电路以在制造和制造期间保护集成电路（IC）。 ESD检测电路通过检测超过ESD阈值电压的电源轨和接地轨之间的电压尖峰来检测ESD事件。 响应于检测到ESD事件，ESD钳位电路被激活以释放ESD事件，从而保护IC免受ESD事件的损害。 通过基于ESD阈值电压检测ESD事件，与基于电压尖峰的上升时间检测ESD事件相反，可以防止ESD钳位电路丢失与缓慢上升时间相关联的电压尖峰或错误地 由与快速上升时间相关联的正常上电电压激活。
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公开(公告)号：US20130286518A1
公开(公告)日：2013-10-31
申请号：US13929933
申请日：2013-06-28
Applicant: RF Micro Devices, Inc.
Inventor： Nathaniel Peachey , Joseph Hubert Colles , Jeffrey D. Potts
IPC: H02H9/04
CPC classification number: G11C7/12 , G11C5/02 , G11C5/06 , G11C5/147 , G11C7/02 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C13/04 , H01L23/60 , H01L2924/0002 , H02H9/041 , H01L2924/00
Abstract: The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.
Abstract translation: 所描述的装置，系统和方法包括具有闩锁的静电放电夹具，以防止电抗放电保护电路响应于电源轨的波动而错误触发。
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公开(公告)号：US09972999B2
公开(公告)日：2018-05-15
申请号：US14819507
申请日：2015-08-06
Applicant: RF Micro Devices, Inc.
Inventor： Nathaniel Peachey
Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. In this regard, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. In one aspect, an ESD voltage detection circuitry activates an ESD clamping circuitry when an ESD voltage associated with faster voltage rise time is detected between a supply rail and a ground rail. In another aspect, an operation voltage detection circuitry deactivates the ESD clamping circuitry when an operation voltage associated with slower voltage rise time is detected between the supply rail and the ground rail. By differentiating the ESD voltage from the operation voltage based on respective voltage rise times, it is possible to prevent the ESD clamping circuitry from missing the ESD voltage associated with the faster voltage rise time or being falsely activated by the operation voltage associated with the slower voltage rise time.
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Patent Agency Ranking
公开(公告)号：US20160043542A1
公开(公告)日：2016-02-11
申请号：US14819507
申请日：2015-08-06
Applicant: RF Micro Devices, Inc.
Inventor： Nathaniel Peachey
IPC: H02H9/02
Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. In this regard, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. In one aspect, an ESD voltage detection circuitry activates an ESD clamping circuitry when an ESD voltage associated with faster voltage rise time is detected between a supply rail and a ground rail. In another aspect, an operation voltage detection circuitry deactivates the ESD clamping circuitry when an operation voltage associated with slower voltage rise time is detected between the supply rail and the ground rail. By differentiating the ESD voltage from the operation voltage based on respective voltage rise times, it is possible to prevent the ESD clamping circuitry from missing the ESD voltage associated with the faster voltage rise time or being falsely activated by the operation voltage associated with the slower voltage rise time.
Abstract translation: 公开了一种静电放电（ESD）保护电路。 在这方面，提供ESD保护电路以保护集成电路（IC）免受ESD事件的影响。 在一个方面，当在电源轨和地轨之间检测到与更快的电压上升时间相关联的ESD电压时，ESD电压检测电路激活ESD钳位电路。 在另一方面，当在电源轨和接地轨之间检测到与较慢电压上升时间相关联的操作电压时，操作电压检测电路使ESD钳位电路去激活。 通过基于相应的电压上升时间来区分ESD电压与工作电压，可以防止ESD钳位电路丢失与较快的电压上升时间相关联的ESD电压，或者由与较低电压相关联的操作电压被错误地激活 上升时间。
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公开(公告)号：US08829981B2
公开(公告)日：2014-09-09
申请号：US13889583
申请日：2013-05-08
Applicant: RF Micro Devices, Inc.
Inventor： Nathaniel Peachey , Ralph Christopher Nieri
Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.
Abstract translation: 自偏压晶体管开关电路包括主晶体管，偏置晶体管，第一电容器和第二电容器。 主晶体管的主体通过绝缘层与主晶体管的栅极，漏极和源极隔离。 第一电容器耦合在主晶体管的源极和栅极之间。 第二电容器耦合在主晶体管的源极和主体之间。 主晶体管的主体和漏极耦合在一起。 偏置晶体管的栅极和漏极耦合到主晶体管的栅极。 偏置晶体管的漏极耦合到主晶体管的漏极。 自偏置晶体管开关电路适于在主晶体管的漏极处接收振荡信号，并且使用振荡信号来适当地偏置主晶体管。
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公开(公告)号：US20140091858A1
公开(公告)日：2014-04-03
申请号：US13889583
申请日：2013-05-08
Applicant: RF MICRO DEVICES, INC.
Inventor： Nathaniel Peachey , Ralph Christopher Nieri
IPC: G05F3/16
Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.
Abstract translation: 自偏压晶体管开关电路包括主晶体管，偏置晶体管，第一电容器和第二电容器。 主晶体管的主体通过绝缘层与主晶体管的栅极，漏极和源极隔离。 第一电容器耦合在主晶体管的源极和栅极之间。 第二电容器耦合在主晶体管的源极和主体之间。 主晶体管的主体和漏极耦合在一起。 偏置晶体管的栅极和漏极耦合到主晶体管的栅极。 偏置晶体管的漏极耦合到主晶体管的漏极。 自偏置晶体管开关电路适于在主晶体管的漏极处接收振荡信号，并且使用振荡信号来适当地偏置主晶体管。
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公开(公告)号：US10461529B2
公开(公告)日：2019-10-29
申请号：US15079554
申请日：2016-03-24
Applicant: RF Micro Devices, Inc.
Inventor： Muhammad Iqbal Chaudhry , Nathaniel Peachey
IPC: H02H9/04
Abstract: Aspects disclosed herein include trigger circuitry for electrostatic discharge (ESD) protection. In this regard, in one aspect, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. Trigger circuitry, which includes a voltage divider for example, divides a voltage spike between a supply rail and a ground rail to provide a trigger voltage. An ESD clamping circuitry is activated to discharge the voltage spike when the trigger voltage is determined to exceed an ESD threshold voltage, thus protecting the IC from being damaged by the voltage spike. By activating the ESD clamping circuitry based on the trigger voltage divided from the voltage spike, it is possible to adapt the ESD protection circuit to provide ESD protection based on different ESD threshold voltages, thus making it possible to deploy the ESD protection circuit on ICs having different ESD protection requirements.
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公开(公告)号：US09244478B2
公开(公告)日：2016-01-26
申请号：US14455346
申请日：2014-08-08
Applicant: RF Micro Devices, Inc.
Inventor： Nathaniel Peachey , Ralph Christopher Nieri
Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.
Abstract translation: 自偏压晶体管开关电路包括主晶体管，偏置晶体管，第一电容器和第二电容器。 主晶体管的主体通过绝缘层与主晶体管的栅极，漏极和源极隔离。 第一电容器耦合在主晶体管的源极和栅极之间。 第二电容器耦合在主晶体管的源极和主体之间。 主晶体管的主体和漏极耦合在一起。 偏置晶体管的栅极和漏极耦合到主晶体管的栅极。 偏置晶体管的漏极耦合到主晶体管的漏极。 自偏置晶体管开关电路适于在主晶体管的漏极处接收振荡信号，并且使用振荡信号来适当地偏置主晶体管。
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