公开(公告)号：US20220165880A1

公开(公告)日：2022-05-26

申请号：US17666501

申请日：2022-02-07

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Kun-Huang Yu ,  Ying-Shiou Lin ,  Chu-Feng Chen ,  Chung-Yu Hung ,  Yi-Rong Tu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, and a drift oxide region. The semiconductor layer is formed on a substrate, wherein the semiconductor layer has at least one trench. The well is formed in the semicoducotor layer. The body region is formed in the well. The gate is formed on the well, and is in contact with the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a bottom surface of the trench.

公开(公告)号：US20210135005A1

公开(公告)日：2021-05-06

申请号：US17148360

申请日：2021-01-13

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Kun-Huang Yu

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L21/265

Abstract: A high voltage device includes: a crystalline silicon layer, a well, a body region, a gate, a source, and a drain. The body region has a P-type conductivity type, and is formed in the well. The gate is located on and in contact with the well. The source and the drain have an N-type conductivity type, and are located below, outside, and at different sides of the gate, and are located in the body region and the well respectively. An inverse region is defined in the body region between the source and the well, to serve as an inverse current channel in an ON operation. The inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*1013 atoms/cm2. Adrift region is defined in the well, between the body region and the drain, to serve as a drift current channel in an ON operation.

公开(公告)号：US10600908B2

公开(公告)日：2020-03-24

申请号：US15937741

申请日：2018-03-27

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L21/265 ,  H01L21/266

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a semiconductor substrate, and includes: a gate, a source, a drain, and at least one plug plate electrode. The plug plate electrode is in direct contact with the gate, and is electrically connected to the gate. The plug plate electrode extends downwards from the bottom of the gate to the semiconductor substrate, through a current vertical height of a conductive current when the high voltage is ON. The plug plate electrode is between the source and the drain in a lateral direction. The plug plate electrode includes a dielectric layer and a conductive layer.

公开(公告)号：US10600895B2

公开(公告)日：2020-03-24

申请号：US16278698

申请日：2019-02-18

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Kuo-Hsuan Lo ,  Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/423 ,  H01L29/06 ,  H01L29/872

Abstract: The invention provides a power device, which includes: an operation layer, including a top surface, a body region and a drift region, the body region and the drift region being connected in a lateral direction, to form a PN junction along a channel width direction between the body region and the drift region; a gate, formed on the top surface, and the PN junction is located under the gate; a source, formed in a portion of the operation layer between the body region and the top surface; a drain, formed in another portion of the operation layer between the drift region and the top surface; a first conduction portion, formed on the top surface for electrically connecting the source; a conduction layer, formed on the first conduction portion and electrically connected to the source via the first conduction portion; and a second conduction portion, formed on the top surface and between the conduction layer and the drift region in a thickness direction, for electrically connecting the drift region and the conduction layer, wherein a Schottky diode is formed by the second conduction portion and the drift region.

公开(公告)号：US20200066878A1

公开(公告)日：2020-02-27

申请号：US16447820

申请日：2019-06-20

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/266 ,  H01L21/8234

Abstract: A MOS device has a reduced ON-resistance; the MOS device has a first lightly doped diffusion (LDD) region which is longer than a second LDD region thereof, and the impurity concentration of the second LDD region is higher than that of the first LDD region. Another MOS device has a spacer layer on a drain sidewall of the gate but does not have a spacer layer on a source sidewall of the gate, wherein the drain sidewall is a sidewall of the gate conductive layer that is adjacent to the drain, and the source sidewall is a sidewall of the gate conductive layer that is adjacent to the source. The MOS device has a higher breakdown voltage, lower ON-resistance, and mitigates the threshold voltage roll-off and other short channel effects.

公开(公告)号：US10418482B2

公开(公告)日：2019-09-17

申请号：US16057725

申请日：2018-08-07

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L21/266 ,  H01L29/10 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66

Abstract: A high voltage device is formed in a semiconductor substrate, and includes: a first deep well, a lateral lightly doped region, a high voltage well, an isolation region, a body region, a gate, a source, a drain, and a first isolation well. The first deep well and the first isolation well are for electrical isolating the high voltage device from neighboring devices below a top surface of the semiconductor substrate. The lateral lightly doped region is located between the first deep well and the high voltage well in a vertical direction, and the lateral lightly doped region contacts the first deep well and the high voltage well. The lateral lightly doped region is for reducing an inner capacitance of the high voltage device when the high voltage device operates, to improve transient response.

公开(公告)号：US10236376B2

公开(公告)日：2019-03-19

申请号：US16037981

申请日：2018-07-17

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.

公开(公告)号：US20180190773A1

公开(公告)日：2018-07-05

申请号：US15622227

申请日：2017-06-14

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Ying-Shiou Lin

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/74 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/74 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device having mitigated threshold voltage roll-off and a threshold voltage roll-off mitigation method therefor. The MOS device includes: a substrate, a well region, an isolation region, a gate, two LDDs (Lightly-Doped-Drains), a source, a drain and a compensation doped region. The compensation doped region is substantially in contact with at least a part of a recessed portion along the channel length direction. Viewing from a cross-section view, at a boundary where the compensation doped region is in contact with the isolation region along the channel length direction, the compensation doped region has two doped region widths along the channel width direction, wherein, the two doped region widths of the compensation doped region are both not greater than 10% of the width of the operation region. Two doped region widths are defined as distances within an interior part and an exterior part of the operation region, respectively.

公开(公告)号：US20170110575A1

公开(公告)日：2017-04-20

申请号：US15192741

申请日：2016-06-24

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L21/76205 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.

公开(公告)号：US10923589B2

公开(公告)日：2021-02-16

申请号：US16542268

申请日：2019-08-15

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Kun-Huang Yu

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/167 ,  H01L29/36 ,  H01L21/02 ,  H01L21/762 ,  H01L21/265

Abstract: A high voltage device includes: a crystalline silicon layer, a well, a body region, a gate, a source, and a drain. The body region has a P-type conductivity type, and is formed in the well. The gate is located on and in contact with the well. The source and the drain have an N-type conductivity type, and are located below, outside, and at different sides of the gate, and are located in the body region and the well respectively. An inverse region is defined in the body region between the source and the well, to serve as an inverse current channel in an ON operation. The inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*1013 atoms/cm2. Adrift region is defined in the well, between the body region and the drain, to serve as a drift current channel in an ON operation.