公开(公告)号：US20180191247A1

公开(公告)日：2018-07-05

申请号：US15587742

申请日：2017-05-05

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Kuo-Hsuan Lo ,  Tsung-Yi Huang

IPC: H02M3/156 ,  H01L29/739 ,  H01L29/10 ,  H01L29/872

CPC classification number: H01L29/7395 ,  H01L29/0619 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/782 ,  H01L29/7835 ,  H01L29/872

Abstract: The invention provides a power device, which includes: an operation layer, including a top surface, a body region and a drift region, the body region and the drift region being connected in a lateral direction, to form a PN junction along a channel width direction between the body region and the drift region; a gate, formed on the top surface, and the PN junction is located under the gate; a source, formed in a portion of the operation layer between the body region and the top surface; a drain, formed in another portion of the operation layer between the drift region and the top surface; a first conduction portion, formed on the top surface for electrically connecting the source; a conduction layer, formed on the first conduction portion and electrically connected to the source via the first conduction portion; and a second conduction portion, formed on the top surface and between the conduction layer and the drift region in a thickness direction, for electrically connecting the drift region and the conduction layer, wherein a Schottky diode is formed by the second conduction portion and the drift region.

公开(公告)号：US20230045843A1

公开(公告)日：2023-02-16

申请号：US17749071

申请日：2022-05-19

Applicant: Richtek Technology Corporation

Inventor： Yu-Ting Yeh ,  Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/765 ,  H01L29/66

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a field oxide region, and a self-aligned drift region. The field oxide region is formed on an upper surface of the semiconductor layer, wherein the field oxide region is located between the gate and the drain. The field oxide region is formed by steps including a chemical mechanical polish (CMP) process step. The self-aligned drift region is formed in the semiconductor layer, wherein the self-aligned drift region is entirely located vertically below and in contact with the field oxide region.

公开(公告)号：US10600895B2

公开(公告)日：2020-03-24

申请号：US16278698

申请日：2019-02-18

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Kuo-Hsuan Lo ,  Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/423 ,  H01L29/06 ,  H01L29/872

Abstract: The invention provides a power device, which includes: an operation layer, including a top surface, a body region and a drift region, the body region and the drift region being connected in a lateral direction, to form a PN junction along a channel width direction between the body region and the drift region; a gate, formed on the top surface, and the PN junction is located under the gate; a source, formed in a portion of the operation layer between the body region and the top surface; a drain, formed in another portion of the operation layer between the drift region and the top surface; a first conduction portion, formed on the top surface for electrically connecting the source; a conduction layer, formed on the first conduction portion and electrically connected to the source via the first conduction portion; and a second conduction portion, formed on the top surface and between the conduction layer and the drift region in a thickness direction, for electrically connecting the drift region and the conduction layer, wherein a Schottky diode is formed by the second conduction portion and the drift region.

公开(公告)号：US12250834B2

公开(公告)日：2025-03-11

申请号：US17737231

申请日：2022-05-05

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng

IPC: H01L29/78 ,  H01L21/765 ,  H10D30/01 ,  H10D30/65 ,  H10D62/17 ,  H10D64/00 ,  H10D84/00

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.

公开(公告)号：US12107160B2

公开(公告)日：2024-10-01

申请号：US17726515

申请日：2022-04-21

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng ,  Chien-Wei Chiu

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L21/76202 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66681

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

公开(公告)号：US20230253494A1

公开(公告)日：2023-08-10

申请号：US17847053

申请日：2022-06-22

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Yu-Ting Yeh ,  Chu-Feng Chen ,  Wu-Te Weng

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/402 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/66681

Abstract: A high voltage device includes: a semiconductor layer, a well, a drift oxide region, a body region, a gate, a source, a drain, and a field plate. The well has a first conductivity type, and is formed in a semiconductor layer. The drift oxide region is formed on the semiconductor layer. The body region has a second conductivity type, and is formed in the semiconductor layer, wherein the body region and a drift region are connected in a channel direction. The gate is formed on the semiconductor layer. The source and the drain have the first conductivity type, and are formed in the semiconductor layer, wherein the source and the drain are in the body region and the well, respectively. The field plate is formed on and connected with the drift oxide region, wherein the field plate is electrically conductive and has a temperature coefficient (TC) not higher than 4 ohm/° C.

公开(公告)号：US20230046174A1

公开(公告)日：2023-02-16

申请号：US17737231

申请日：2022-05-05

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/10 ,  H01L21/765 ,  H01L29/66

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.

公开(公告)号：US20220376110A1

公开(公告)日：2022-11-24

申请号：US17726515

申请日：2022-04-21

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng ,  Chien-Wei Chiu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L21/762 ,  H01L29/66

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

公开(公告)号：US20190181253A1

公开(公告)日：2019-06-13

申请号：US16278698

申请日：2019-02-18

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Kuo-Hsuan Lo ,  Tsung-Yi Huang

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7395 ,  H01L29/0619 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/782 ,  H01L29/7835 ,  H01L29/872

Abstract: The invention provides a power device, which includes: an operation layer, including a top surface, a body region and a drift region, the body region and the drift region being connected in a lateral direction, to form a PN junction along a channel width direction between the body region and the drift region; a gate, formed on the top surface, and the PN junction is located under the gate; a source, formed in a portion of the operation layer between the body region and the top surface; a drain, formed in another portion of the operation layer between the drift region and the top surface; a first conduction portion, formed on the top surface for electrically connecting the source; a conduction layer, formed on the first conduction portion and electrically connected to the source via the first conduction portion; and a second conduction portion, formed on the top surface and between the conduction layer and the drift region in a thickness direction, for electrically connecting the drift region and the conduction layer, wherein a Schottky diode is formed by the second conduction portion and the drift region.