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公开(公告)号:US20240345922A1
公开(公告)日:2024-10-17
申请号:US18629677
申请日:2024-04-08
Applicant: Rambus Inc.
Inventor: Aws SHALLAL , Chen CHEN
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/1658
Abstract: A serial presence detect (SPD) device includes nonvolatile memory to store SPD information. Parity information suitable for single error correct and double error detect (SEC-DED) is also stored in association with the SPD information in the nonvolatile memory. The combination of SPD information and parity information is organized into codewords addressable at each memory location. During an initialization period occurring after a power on reset and before the SPD device is accepting I2C commands, the SPD device checks each memory location (codeword) for errors. Each error detected is counted to provide an indicator of device health. Before the initialization period expires, the SPD device writes a corrected codeword back to the nonvolatile memory.
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公开(公告)号:US20230021898A1
公开(公告)日:2023-01-26
申请号:US17857241
申请日:2022-07-05
Applicant: Rambus Inc.
Inventor: Aws SHALLAL , Chen CHEN
Abstract: A serial presence detect (SPD) device includes nonvolatile memory to store SPD information. Parity information suitable for single error correct and double error detect (SEC-DED) is also stored in association with the SPD information in the nonvolatile memory. The combination of SPD information and parity information is organized into codewords addressable at each memory location. During an initialization period occurring after a power on reset and before the SPD device is accepting I2C commands, the SPD device checks each memory location (codeword) for errors. Each error detected is counted to provide an indicator of device health. Before the initialization period expires, the SPD device writes a corrected codeword back to the nonvolatile memory.
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公开(公告)号:US20250004650A1
公开(公告)日:2025-01-02
申请号:US18775507
申请日:2024-07-17
Applicant: Rambus Inc.
Inventor: Aws SHALLAL , Chen CHEN
IPC: G06F3/06
Abstract: A serial presence detect (SPD) device includes a region of nonvolatile memory for SPD data and an additional region for other (e.g., vendor) use. The additional region may be subdivided into write protect regions that can be individually and independently write protected. To configure the write protection, a password key scheme is used to enter a mode whereby the write protection attributes may be configured. Another password key scheme is used to exit the write protection configuration mode.
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公开(公告)号:US20230014101A1
公开(公告)日:2023-01-19
申请号:US17857252
申请日:2022-07-05
Applicant: Rambus Inc.
Inventor: Aws SHALLAL , Chen CHEN
IPC: G06F3/06
Abstract: A serial presence detect (SPD) device includes a region of nonvolatile memory for SPD data and an additional region for other (e.g., vendor) use. The additional region may be subdivided into write protect regions that can be individually and independently write protected. To configure the write protection, a password key scheme is used to enter a mode whereby the write protection attributes may be configured. Another password key scheme is used to exit the write protection configuration mode.
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公开(公告)号:US20170109058A1
公开(公告)日:2017-04-20
申请号:US15156691
申请日:2016-05-17
Applicant: Rambus Inc.
Inventor: Aws SHALLAL , Michael MILLER , Stephen HORN
CPC classification number: G06F3/0613 , G06F3/0611 , G06F3/065 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F3/0685 , G06F11/00 , G06F12/0802 , G06F13/1668 , G06F13/1673 , G06F2212/1024 , G06F2212/205 , G11C5/04 , G11C7/1051 , G11C11/005 , G11C14/0009
Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.
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