公开(公告)号：US20170109058A1

公开(公告)日：2017-04-20

申请号：US15156691

申请日：2016-05-17

Applicant: Rambus Inc.

Inventor： Aws SHALLAL ,  Michael MILLER ,  Stephen HORN

IPC: G06F3/06 ,  G11C14/00

CPC classification number: G06F3/0613 ,  G06F3/0611 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F11/00 ,  G06F12/0802 ,  G06F13/1668 ,  G06F13/1673 ,  G06F2212/1024 ,  G06F2212/205 ,  G11C5/04 ,  G11C7/1051 ,  G11C11/005 ,  G11C14/0009

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.