公开(公告)号：US20200349005A1

公开(公告)日：2020-11-05

申请号：US16881859

申请日：2020-05-22

Applicant: Rambus Inc.

Inventor： Michael MILLER ,  Stephen MAGEE ,  John Eric LINSTADT

IPC: G06F11/10 ,  G06F3/06

Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

公开(公告)号：US20180357125A1

公开(公告)日：2018-12-13

申请号：US15990078

申请日：2018-05-25

Applicant: Rambus Inc.

Inventor： Michael MILLER ,  Stephen MAGEE ,  John Eric LINSTADT

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0673 ,  G06F11/1048

Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

公开(公告)号：US20170109058A1

公开(公告)日：2017-04-20

申请号：US15156691

申请日：2016-05-17

Applicant: Rambus Inc.

Inventor： Aws SHALLAL ,  Michael MILLER ,  Stephen HORN

IPC: G06F3/06 ,  G11C14/00

CPC classification number: G06F3/0613 ,  G06F3/0611 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F11/00 ,  G06F12/0802 ,  G06F13/1668 ,  G06F13/1673 ,  G06F2212/1024 ,  G06F2212/205 ,  G11C5/04 ,  G11C7/1051 ,  G11C11/005 ,  G11C14/0009

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.