公开(公告)号：US20240211420A1

公开(公告)日：2024-06-27

申请号：US18569451

申请日：2022-06-20

Applicant: Rambus Inc.

Inventor： Steven C. WOO ,  Dongyun LEE

IPC: G06F13/16

CPC classification number: G06F13/1673 ,  G06F13/1689

Abstract: A four-channel memory module includes four independent memory channels and dual channel memory devices. The channels of the dual channel memory are accessed independently. Thus, the four channels for accessing the memory module each access one channel of a first set and a second set of dual channel memory devices on the module. Dual channel data buffer devices are also included on the module. The dual channel data buffer devices also retime data strobe signals for accesses to/from the sets of dual channel memory devices.

公开(公告)号：US20230125262A1

公开(公告)日：2023-04-27

申请号：US17963065

申请日：2022-10-10

Applicant: Rambus Inc.

Inventor： Mark D. KELLAM ,  Dongyun LEE ,  Thomas VOGELSANG ,  Steven C. WOO

IPC: G02B6/293 ,  G02B6/12 ,  H04B10/50

Abstract: Command/address and timing information is distributed to buffer integrated circuits on a module using multiple wavelengths of light modulated with the same information. Each individual wavelength of modulated light carrying command/address information is received by a corresponding single buffer device that deserializes the command/address information and communicates it electrically to memory devices(s). Likewise, each individual wavelength of modulated light carrying timing/synchronization/clock information is received by a corresponding single buffer device and used to synchronize accesses to the memory device(s). Thus, multiple buffer integrated circuits on a module each receive information from the CPU using different wavelengths of light transmitted on the same waveguide.

公开(公告)号：US20250061935A1

公开(公告)日：2025-02-20

申请号：US18796915

申请日：2024-08-07

Applicant: Rambus Inc.

Inventor： Dongyun LEE ,  Mark D. KELLAM ,  Joohee KIM

IPC: G11C11/4076 ,  G11C11/4074 ,  G11C11/419

Abstract: An interposer interconnecting a first integrated circuit and a second integrated circuit includes active circuitry. The “active” interposer converts high-speed signals into lower-speed, but more parallelized, signals for transmission across the active interposer. The parallelized signals may be buffered or amplified at intervals while crossing the active interposer. The high-speed to low-speed, and back, conversions may be performed by an appropriately configured and controlled multiplexer/demultiplexer circuitry The supply voltages for some interposer circuits may be different than the supply voltages for the interfaces with the first and second integrated circuit. One or more of the interconnected integrated circuits may supply, and/or calibrate the supply voltages for the interposer circuitry. Timing signals provided by one or more of the interconnected integrated circuits may also be calibrated using circuitry on the active interposer.

公开(公告)号：US20240370361A1

公开(公告)日：2024-11-07

申请号：US18687116

申请日：2022-08-23

Applicant: Rambus Inc.

Inventor： Joohee KIM ,  Dongyun LEE ,  Steven C. WOO

IPC: G06F12/02

Abstract: Multiple (e.g., four) memory devices on a module are connected to a common pair of differential data strobe signal conductors. The common pair of differential data strobe conductors are also coupled to a memory controller to time the transmission of data to the multiple memory devices and to time the reception of data from the memory devices. The controller calibrates two or more different data transmission delays relative to its transmission of a write data strobe signal on the common pair of differential data strobe conductors. The controller also calibrates to account for two or more different data reception delays (skew) relative to its reception of a read data strobe signal on the common pair of differential data strobe conductors.

公开(公告)号：US20240272982A1

公开(公告)日：2024-08-15

申请号：US18569503

申请日：2022-06-21

Applicant: Rambus Inc.

Inventor： Steven C. WOO ,  Dongyun LEE

IPC: G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/1004 ,  G06F11/1068

Abstract: A four-channel memory module includes four independent twenty (20) data bit memory channels and dual channel memory devices. The channels of the dual channel memory are accessed independently. Thus, the four channels for accessing the memory module each access one channel of a first set and a second set of dual channel memory devices on the module. Error detection and correction codeword configurations and schemes can implement chipkill, Single symbol data correct/double symbol data detect (SSDC/DSDD). Single symbol data correct with fewer memory devices may also be implemented. Error detection and correction codeword configurations and schemes may be switched in response to detecting a failed device, signal line, or memory channel.

公开(公告)号：US20230099474A1

公开(公告)日：2023-03-30

申请号：US17941792

申请日：2022-09-09

Applicant: Rambus Inc.

Inventor： Dongyun LEE ,  Carl W. WERNER ,  Torsten PARTSCH

IPC: H01L25/065 ,  G11C8/12 ,  G11C7/10

Abstract: An interconnected stack of Dynamic Random Access Memory (DRAM) die has a base die and DRAM dies. The base die is interconnected vertically with the DRAM dies using through-silicon via (TSV) connections that carry data and control signals throughout the stack. The data signals of the DRAM dies are interconnected vertically to the base die using separate, non-overlapping, sets of TSVs. In a first configuration, each die in the stack is accessed using unique chip identification numbers. In a second configuration, a single chip identification number is used to access two or more dies in the stack. At least one bit of the chip identification number may be used in determining the row being accessed. Data communicated with dies in the stack may be communicated with the base die using non-overlapping sets of data signal connections.