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公开(公告)号:US20240428835A1
公开(公告)日:2024-12-26
申请号:US18767988
申请日:2024-07-10
Applicant: Rambus Inc.
Inventor: Andrew M. Fuller , Robert E. Palmer , Thomas J. Giovannini , Michael D. Bucher , Thoai Thai Le
Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.
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公开(公告)号:US10067519B2
公开(公告)日:2018-09-04
申请号:US15626096
申请日:2017-06-17
Applicant: Rambus Inc.
Inventor: Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
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公开(公告)号:US20170351282A1
公开(公告)日:2017-12-07
申请号:US15626096
申请日:2017-06-17
Applicant: Rambus Inc.
Inventor: Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
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公开(公告)号:US20150145581A1
公开(公告)日:2015-05-28
申请号:US14539564
申请日:2014-11-12
Applicant: Rambus Inc.
Inventor: Robert E. Palmer , Michael D. Bucher , Andrew M. Fuller
CPC classification number: H03K5/131 , H03K5/135 , H03K2005/00058
Abstract: A controllable delay element includes a delay element to provide a variable delay from an input signal to an output signal. The variable delay can be controlled by a digital delay input. The delay element has a delay range that is controlled in response to a delay range input. The delay range of the delay element can be calibrated to a desired range of delays in response to a relative delay between a first timing reference and a second timing reference. A common timing reference is applied to a plurality of receivers and a strobe receiver. The delay through the strobe receiver is adjusted to measure the delay mismatches between the plurality of receivers. The mismatches are used to select a value for the delay through the strobe receiver.
Abstract translation: 可控延迟元件包括延迟元件以提供从输入信号到输出信号的可变延迟。 可变延迟可以通过数字延迟输入来控制。 延迟元件具有响应于延迟范围输入而被控制的延迟范围。 可以响应于第一定时参考和第二定时参考之间的相对延迟,将延迟元件的延迟范围校准到期望的延迟范围。 公共定时参考应用于多个接收机和选通接收机。 通过选通接收机的延迟被调整以测量多个接收机之间的延迟不匹配。 不匹配用于通过选通接收器选择延迟的值。
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公开(公告)号:US12062413B1
公开(公告)日:2024-08-13
申请号:US18234288
申请日:2023-08-15
Applicant: Rambus Inc.
Inventor: Andrew M. Fuller , Robert E. Palmer , Thomas J. Giovannini , Michael D. Bucher , Thoai Thai Le
CPC classification number: G11C7/222 , G11C7/1066 , G11C7/1072 , G11C7/1093
Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.
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公开(公告)号:US20150309517A1
公开(公告)日:2015-10-29
申请号:US14699780
申请日:2015-04-29
Applicant: Rambus Inc.
Inventor: Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
IPC: G05F1/46
Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
Abstract translation: 集成电路包括用于提供调节电压的电压调节器和耦合到未终端传输线的数据输出。 该电路根据数据从电压调节器抽取可变量的功率。 电压调节器包括用于提供数据转变相关电流的第一电流产生电路。
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公开(公告)号:US11763865B1
公开(公告)日:2023-09-19
申请号:US17458215
申请日:2021-08-26
Applicant: Rambus Inc.
Inventor: Andrew Fuller , Robert E. Palmer , Thomas J. Giovannini , Michael D. Bucher , Thoai Thai Le
CPC classification number: G11C7/222 , G11C7/1066 , G11C7/1072 , G11C7/1093
Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.
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公开(公告)号:US11127444B1
公开(公告)日:2021-09-21
申请号:US16995612
申请日:2020-08-17
Applicant: Rambus Inc.
Inventor: Andrew Fuller , Robert E. Palmer , Thomas J. Giovannini , Michael D. Bucher , Thoai Thai Le
Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.
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公开(公告)号:US09684321B2
公开(公告)日:2017-06-20
申请号:US14699780
申请日:2015-04-29
Applicant: Rambus Inc.
Inventor: Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
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公开(公告)号:US09419598B2
公开(公告)日:2016-08-16
申请号:US14539564
申请日:2014-11-12
Applicant: Rambus Inc.
Inventor: Robert E. Palmer , Michael D. Bucher , Andrew M. Fuller
CPC classification number: H03K5/131 , H03K5/135 , H03K2005/00058
Abstract: A controllable delay element includes a delay element to provide a variable delay from an input signal to an output signal. The variable delay can be controlled by a digital delay input. The delay element has a delay range that is controlled in response to a delay range input. The delay range of the delay element can be calibrated to a desired range of delays in response to a relative delay between a first timing reference and a second timing reference. A common timing reference is applied to a plurality of receivers and a strobe receiver. The delay through the strobe receiver is adjusted to measure the delay mismatches between the plurality of receivers. The mismatches are used to select a value for the delay through the strobe receiver.
Abstract translation: 可控延迟元件包括延迟元件以提供从输入信号到输出信号的可变延迟。 可变延迟可以通过数字延迟输入来控制。 延迟元件具有响应于延迟范围输入而被控制的延迟范围。 可以响应于第一定时参考和第二定时参考之间的相对延迟,将延迟元件的延迟范围校准到期望的延迟范围。 公共定时参考应用于多个接收机和选通接收机。 通过选通接收机的延迟被调整以测量多个接收机之间的延迟不匹配。 不匹配用于通过选通接收器选择延迟的值。
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