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公开(公告)号：US10541693B2
公开(公告)日：2020-01-21
申请号：US16242475
申请日：2019-01-08
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC: H03L7/091 , H03K5/156 , H03L7/00 , G11C7/10 , G11C7/22 , H04L7/00 , H04L7/033 , H03L7/08 , H03L7/099 , G11C7/04
Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
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公开(公告)号：US09748960B2
公开(公告)日：2017-08-29
申请号：US14456716
申请日：2014-08-11
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC: H03L7/091 , H03L7/099 , H03L7/00 , G11C7/10 , G11C7/22 , H04L7/033 , H03L7/08 , H04L7/00 , G11C7/04
CPC classification number: H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
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公开(公告)号：US09166838B1
公开(公告)日：2015-10-20
申请号：US14489814
申请日：2014-09-18
Applicant: Rambus Inc.
Inventor： Lei Luo , Barry W. Daly , Kambiz Kaviani , John Cronan Eble, III , John Wilson
CPC classification number: H03K3/013 , G11C5/147 , G11C29/021 , G11C29/022 , G11C29/028 , H04L25/0296 , H04L25/06 , H04L25/08
Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.
Abstract translation: 发射机上的信号以与电源的正节点分离的方式跟踪接地节点上的噪声。 信号从发射机发射到接收机。 在接收机上产生参考电压以跟踪接收机中接地节点上的噪声。 因此，接收信号和参考电压具有基本上相同的噪声特性，这些噪声特性成为当这两个信号彼此进行比较时可以消除的共模噪声。 在另一实施例中，将参考电压与预定校准图案进行比较。 基于采样器输出和预定校准图案之间的差异产生误差信号。 然后使用误差信号来调整参考电压，使得参考电压的直流电平基本上位于接收信号的中间。
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公开(公告)号：US09564879B1
公开(公告)日：2017-02-07
申请号：US14855244
申请日：2015-09-15
Applicant: Rambus Inc.
Inventor： Lei Luo , Barry W. Daly , Kambiz Kaviani , John Cronan Eble, III , John Wilson
CPC classification number: H03K3/013 , G11C5/147 , G11C29/021 , G11C29/022 , G11C29/028 , H04L25/0296 , H04L25/06 , H04L25/08
Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.
Abstract translation: 发射机上的信号以与电源的正节点分离的方式跟踪接地节点上的噪声。 信号从发射机发射到接收机。 在接收机上产生参考电压以跟踪接收机中接地节点上的噪声。 因此，接收信号和参考电压具有基本相同的噪声特性，这些噪声特性成为当这两个信号彼此进行比较时可以消除的共模噪声。 在另一实施例中，将参考电压与预定校准图案进行比较。 基于采样器输出和预定校准图案之间的差异产生误差信号。 然后使用误差信号来调整参考电压，使得参考电压的直流电平基本上位于接收信号的中间。
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公开(公告)号：US20150309517A1
公开(公告)日：2015-10-29
申请号：US14699780
申请日：2015-04-29
Applicant: Rambus Inc.
Inventor： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
IPC: G05F1/46
Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
Abstract translation: 集成电路包括用于提供调节电压的电压调节器和耦合到未终端传输线的数据输出。 该电路根据数据从电压调节器抽取可变量的功率。 电压调节器包括用于提供数据转变相关电流的第一电流产生电路。
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Patent Agency Ranking
公开(公告)号：US20140347108A1
公开(公告)日：2014-11-27
申请号：US14456716
申请日：2014-08-11
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
CPC classification number: H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
Abstract translation: 在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。 芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。
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公开(公告)号：US09684321B2
公开(公告)日：2017-06-20
申请号：US14699780
申请日：2015-04-29
Applicant: Rambus Inc.
Inventor： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
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公开(公告)号：US09294317B1
公开(公告)日：2016-03-22
申请号：US13831993
申请日：2013-03-15
Applicant: Rambus Inc.
Inventor： John Wilson , Lei Luo , Wayne D. Dettloff
IPC: H04L25/03
CPC classification number: H04L25/03878 , H04L25/028 , H04L25/0292 , H04L25/03012 , H04L25/03343
Abstract: AC-coupled termination and equalization, including transmit equalization and/or receive equalization, are combined to create a high bandwidth channel that requires no special coding and consumes no or negligible DC current.
Abstract translation: 包括发射均衡和/或接收均衡在内的AC耦合终端和均衡被组合以产生不需要特殊编码并且消耗不可忽略的DC电流的高带宽信道。
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公开(公告)号：US20140376364A1
公开(公告)日：2014-12-25
申请号：US14236572
申请日：2012-07-20
Applicant: RAMBUS INC.
Inventor： Paul D. Franzon , John Wilson
CPC classification number: H04L41/0686 , G06F11/2007 , H03L7/18 , H03L7/23 , H04L1/0002 , H04L1/22 , H04L41/0659 , H04L41/0668
Abstract: A circuit is provided to facilitate temporal redundancy for inter-chip communication. When an inter-chip communication channel fails, data bits associated with the faulty channel are steered to a non-faulty channel and transmitted via the non-faulty channel together with data bits associated with the non-faulty channel at an increased data rate.
Abstract translation: 提供电路以便于芯片间通信的时间冗余。 当芯片间通信信道发生故障时，与故障信道相关联的数据比特被引导到非故障信道，并且以增加的数据速率与非故障信道相关联的数据比特通过非故障信道发送。
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公开(公告)号：US08867595B1
公开(公告)日：2014-10-21
申请号：US13913743
申请日：2013-06-10
Applicant: Rambus Inc.
Inventor： Lei Luo , Barry W. Daly , Kambiz Kaviani , John Cronan Eble, III , John Wilson
CPC classification number: H03K3/013 , G11C5/147 , G11C29/021 , G11C29/022 , G11C29/028 , H04L25/0296 , H04L25/06 , H04L25/08
Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.
Abstract translation: 发射机上的信号以与电源的正节点分离的方式跟踪接地节点上的噪声。 信号从发射机发射到接收机。 在接收机上产生参考电压以跟踪接收机中接地节点上的噪声。 因此，接收信号和参考电压具有基本上相同的噪声特性，这些噪声特性成为当这两个信号彼此进行比较时可以消除的共模噪声。 在另一实施例中，将参考电压与预定校准图案进行比较。 基于采样器输出和预定校准图案之间的差异产生误差信号。 然后使用误差信号来调整参考电压，使得参考电压的直流电平基本上位于接收信号的中间。
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