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公开(公告)号：US10230384B2
公开(公告)日：2019-03-12
申请号：US15818434
申请日：2017-11-20
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US11239855B2
公开(公告)日：2022-02-01
申请号：US17166919
申请日：2021-02-03
Applicant: Rambus Inc.
Inventor： Shankar Tangirala
Abstract: A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.
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公开(公告)号：US20210250038A1
公开(公告)日：2021-08-12
申请号：US17166919
申请日：2021-02-03
Applicant: Rambus Inc.
Inventor： Shankar Tangirala
Abstract: A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.
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公开(公告)号：US20180167076A1
公开(公告)日：2018-06-14
申请号：US15818434
申请日：2017-11-20
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US12206423B2
公开(公告)日：2025-01-21
申请号：US18092564
申请日：2023-01-03
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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Patent Agency Ranking
公开(公告)号：US11476868B2
公开(公告)日：2022-10-18
申请号：US17153157
申请日：2021-01-20
Applicant: RAMBUS INC.
Inventor： Shankar Tangirala
Abstract: A dual-loop analog to digital converter (ADC) includes an asynchronous inner loop including first and second comparators and a state machine, where outputs of the first and second comparators are coupled to inputs of the state machine, and where outputs of the state machine are cross-coupled to enable ports of the first and second comparators. The ADC includes a synchronous outer loop including a successive approximation register (SAR), a digital to analog converter (DAC), and the first and second comparators, where the outputs of the first and second comparators are coupled to inputs of the SAR, an N-bit output of the SAR is coupled to an N-bit input of the DAC, and a differential output of the DAC is coupled to inputs of the first and second comparators, where a state of the state machine is independent of the state of the SAR.
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公开(公告)号：US11038514B2
公开(公告)日：2021-06-15
申请号：US16885805
申请日：2020-05-28
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US11575386B2
公开(公告)日：2023-02-07
申请号：US17315699
申请日：2021-05-10
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US20210234548A1
公开(公告)日：2021-07-29
申请号：US17153157
申请日：2021-01-20
Applicant: RAMBUS INC.
Inventor： Shankar Tangirala
IPC: H03M1/46
Abstract: A dual-loop analog to digital converter (ADC) includes an asynchronous inner loop including first and second comparators and a state machine, where outputs of the first and second comparators are coupled to inputs of the state machine, and where outputs of the state machine are cross-coupled to enable ports of the first and second comparators. The ADC includes a synchronous outer loop including a successive approximation register (SAR), a digital to analog converter (DAC), and the first and second comparators, where the outputs of the first and second comparators are coupled to inputs of the SAR, an N-bit output of the SAR is coupled to an N-bit input of the DAC, and a differential output of the DAC is coupled to inputs of the first and second comparators, where a state of the state machine is independent of the state of the SAR.
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公开(公告)号：US10707885B2
公开(公告)日：2020-07-07
申请号：US16272236
申请日：2019-02-11
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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