公开(公告)号：US09324726B2

公开(公告)日：2016-04-26

申请号：US14802050

申请日：2015-07-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Kyoko Umeda ,  Akio Nishida

IPC: H01L21/336 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11573

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.

Abstract translation: 提高了半导体器件的性能。 在制造半导体器件的方法中，在存储单元区域中，在半导体衬底的主表面上形成由第一导电膜形成的控制栅电极。 然后，以覆盖控制栅电极的方式形成绝缘膜和第二导电膜，并且将第二导电膜回蚀刻。 结果，第二导电膜经由绝缘膜留在控制栅电极的侧壁上，从而形成存储栅电极。 然后，在外围电路区域中，在半导体衬底的主表面上形成p型阱。 在p型阱上形成第三导电膜。 然后，形成由第三导电膜形成的栅电极。

公开(公告)号：US20160260795A1

公开(公告)日：2016-09-08

申请号：US14992067

申请日：2016-01-11

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Abe ,  Hiraku Chakihara ,  Kyoko Umeda ,  Yoshiyuki Kawashima ,  Kentaro Saito

IPC: H01L49/02 ,  H01L27/115

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/11573

Abstract: In a semiconductor device including a nonvolatile memory, a novel stacked capacitive element is provided. The semiconductor device includes the stacked capacitive element including a first capacitive electrode made of an n-type well region formed in a semiconductor substrate, a second capacitive electrode formed so as to overlap the first capacitive electrode via a first capacitive insulating film, a third capacitive electrode formed so as to overlap the second capacitive electrode via a second capacitive insulating film, and a fourth capacitive electrode formed so as to overlap the third capacitive electrode via a third capacitive insulating film. To the first and third capacitive electrodes, a first potential is applied and, to the second and fourth capacitive electrodes, a second potential different from the first potential is applied.

Abstract translation: 在包括非易失性存储器的半导体器件中，提供了一种新颖的叠层电容元件。 半导体器件包括堆叠的电容元件，其包括由形成在半导体衬底中的n型阱区域构成的第一电容电极，经由第一电容绝缘膜形成为与第一电容电极重叠的第二电容电极，第三电容 电极，其经由第二电容绝缘膜与第二电容电极重叠形成，第四电容电极通过第三电容绝缘膜与第三电容电极重叠形成。 对于第一和第三电容电极，施加第一电位，并且向第二和第四电容电极施加不同于第一电位的第二电位。

公开(公告)号：US20160064402A1

公开(公告)日：2016-03-03

申请号：US14829638

申请日：2015-08-19

Applicant: Renesas Electronics Corporation

Inventor： Kyoko Umeda ,  Yoshiyuki Kawashima ,  Hiraku Chakihara

IPC: H01L27/115 ,  H01L21/3213 ,  H01L21/02 ,  H01L49/02 ,  H01L21/28

CPC classification number: H01L21/32135 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/40 ,  H01L28/60 ,  H01L29/42344 ,  H01L29/66833

Abstract: In method for manufacturing a semiconductor device including a nonvolatile memory, a new method for manufacturing a capacitor element is provided. After working a control gate electrode, a gate insulation film including an electric charge accumulation section, and a memory gate electrode of a memory cell, in order to protect the memory cell, a p-type well of a MISFET is formed in a state the control gate electrode, the gate insulation film, and the memory gate electrode are covered by an insulation film. Also, this insulation film is used as a capacitor insulation film of a laminated type capacitor element.

Abstract translation: 在制造包括非易失性存储器的半导体器件的方法中，提供了一种用于制造电容器元件的新方法。 为了保护存储单元，在加工了控制栅电极，包括电荷累积部分的栅极绝缘膜和存储单元的存储栅极之后，形成MISFET的p型阱，状态为 控制栅电极，栅极绝缘膜和存储栅电极被绝缘膜覆盖。 此外，该绝缘膜用作叠层型电容器元件的电容器绝缘膜。

公开(公告)号：US20160204116A1

公开(公告)日：2016-07-14

申请号：US15073524

申请日：2016-03-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Kyoko Umeda ,  Akio Nishida

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.

公开(公告)号：US20160035734A1

公开(公告)日：2016-02-04

申请号：US14802050

申请日：2015-07-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Kyoko Umeda ,  Akio Nishida

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11573

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.

Abstract translation: 提高了半导体器件的性能。 在制造半导体器件的方法中，在存储单元区域中，在半导体衬底的主表面上形成由第一导电膜形成的控制栅电极。 然后，以覆盖控制栅电极的方式形成绝缘膜和第二导电膜，并且将第二导电膜回蚀刻。 结果，第二导电膜经由绝缘膜留在控制栅电极的侧壁上，从而形成存储栅电极。 然后，在外围电路区域中，在半导体衬底的主表面上形成p型阱。 在p型阱上形成第三导电膜。 然后，形成由第三导电膜形成的栅电极。