公开(公告)号：US09356110B2

公开(公告)日：2016-05-31

申请号：US14173074

申请日：2014-02-05

Applicant: Renesas Electronics Corporation

Inventor： Masao Inoue ,  Yoshiki Maruyama ,  Akio Nishida ,  Yorinobu Kunimune ,  Kota Funayama

IPC: H01L21/28 ,  H01L29/40 ,  H01L29/49 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/4925 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/28035 ,  H01L21/28176 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66825

Abstract: To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film (21) on a substrate (10); forming an interlayer oxide layer (22) on a surface of the first polysilicon film (21); forming a second polysilicon film (23) in contact with the interlayer oxide layer (22) above the first polysilicon film (21); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film (23).

Abstract translation: 为了控制层叠多晶硅膜上的晶粒生长，提供了制造半导体器件的方法。 该方法包括：在衬底（10）上形成第一多晶硅膜（21）; 在所述第一多晶硅膜（21）的表面上形成层间氧化物层（22）; 形成与第一多晶硅膜（21）上方的层间氧化物层（22）接触的第二多晶硅膜（23）。 在形成第二多晶硅膜（23）之后，在含氮气体气氛中，在高于第一和第二多晶硅膜的成膜温度的温度下进行退火。

公开(公告)号：US09349743B2

公开(公告)日：2016-05-24

申请号：US14804305

申请日：2015-07-20

Applicant: Renesas Electronics Corporation

Inventor： Nobuto Nakanishi ,  Yoshiyuki Kawashima ,  Akio Nishida

IPC: H01L21/28 ,  H01L27/115 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/51 ,  H01L21/3213 ,  H01L29/45 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/31053 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/456 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

Abstract: To provide a semiconductor device having improved reliability. A semiconductor device is provided forming a control gate electrode for memory cell on a semiconductor substrate via a first insulating film; forming a memory gate electrode for memory cell, which is adjacent to the control gate electrode, on the semiconductor substrate via a second insulating film having a charge storage portion; forming n− type semiconductor regions for source or drain in the semiconductor substrate by ion implantation; forming sidewall spacers on the side wall of the control gate electrode and the memory gate electrode; forming n+ type semiconductor regions for source or drain in the semiconductor substrate by ion implantation; and removing an upper portion of the second insulating film present between the control gate electrode and the memory gate electrode. A removal length of the second insulating film is larger than the depth of the n+ type semiconductor regions.

Abstract translation: 提供具有提高的可靠性的半导体器件。 提供一种通过第一绝缘膜在半导体衬底上形成用于存储单元的控制栅电极的半导体器件; 通过具有电荷存储部分的第二绝缘膜，在半导体衬底上形成与控制栅电极相邻的用于存储单元的存储栅电极; 通过离子注入在半导体衬底中形成用于源极或漏极的n-型半导体区域; 在控制栅电极和存储栅电极的侧壁上形成侧壁间隔物; 通过离子注入在半导体衬底中形成用于源极或漏极的n +型半导体区域; 以及去除存在于控制栅电极和存储栅电极之间的第二绝缘膜的上部。 第二绝缘膜的去除长度大于n +型半导体区域的深度。

公开(公告)号：US20160204116A1

公开(公告)日：2016-07-14

申请号：US15073524

申请日：2016-03-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Kyoko Umeda ,  Akio Nishida

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.

公开(公告)号：US20160043098A1

公开(公告)日：2016-02-11

申请号：US14804305

申请日：2015-07-20

Applicant: Renesas Electronics Corporation

Inventor： Nobuto Nakanishi ,  Yoshiyuki Kawashima ,  Akio Nishida

IPC: H01L27/115 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/423 ,  H01L29/51 ,  H01L21/3213 ,  H01L29/45 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/31053 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/456 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

Abstract: To provide a semiconductor device having improved reliability. A semiconductor device is provided forming a control gate electrode for memory cell on a semiconductor substrate via a first insulating film; forming a memory gate electrode for memory cell, which is adjacent to the control gate electrode, on the semiconductor substrate via a second insulating film having a charge storage portion; forming n− type semiconductor regions for source or drain in the semiconductor substrate by ion implantation; forming sidewall spacers on the side wall of the control gate electrode and the memory gate electrode; forming n+ type semiconductor regions for source or drain in the semiconductor substrate by ion implantation; and removing an upper portion of the second insulating film present between the control gate electrode and the memory gate electrode. A removal length of the second insulating film is larger than the depth of the n+ type semiconductor regions.

Abstract translation: 提供具有提高的可靠性的半导体器件。 提供一种通过第一绝缘膜在半导体衬底上形成用于存储单元的控制栅电极的半导体器件; 通过具有电荷存储部分的第二绝缘膜，在半导体衬底上形成与控制栅电极相邻的用于存储单元的存储栅电极; 通过离子注入在半导体衬底中形成用于源极或漏极的n-型半导体区域; 在控制栅电极和存储栅电极的侧壁上形成侧壁间隔物; 通过离子注入在半导体衬底中形成用于源极或漏极的n +型半导体区域; 以及去除存在于控制栅电极和存储栅电极之间的第二绝缘膜的上部。 第二绝缘膜的去除长度大于n +型半导体区域的深度。

公开(公告)号：US20160035734A1

公开(公告)日：2016-02-04

申请号：US14802050

申请日：2015-07-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Kyoko Umeda ,  Akio Nishida

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11573

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.

Abstract translation: 提高了半导体器件的性能。 在制造半导体器件的方法中，在存储单元区域中，在半导体衬底的主表面上形成由第一导电膜形成的控制栅电极。 然后，以覆盖控制栅电极的方式形成绝缘膜和第二导电膜，并且将第二导电膜回蚀刻。 结果，第二导电膜经由绝缘膜留在控制栅电极的侧壁上，从而形成存储栅电极。 然后，在外围电路区域中，在半导体衬底的主表面上形成p型阱。 在p型阱上形成第三导电膜。 然后，形成由第三导电膜形成的栅电极。

公开(公告)号：US08797791B2

公开(公告)日：2014-08-05

申请号：US13865279

申请日：2013-04-18

Applicant: Renesas Electronics Corporation

Inventor： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC: H01L29/788 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H03K19/00 ,  H01L27/092 ,  H01L27/11 ,  H01L27/105 ,  G11C11/412

CPC classification number: G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract translation: 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US20160064226A1

公开(公告)日：2016-03-03

申请号：US14829614

申请日：2015-08-18

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Akio Nishida

IPC: H01L21/28 ,  H01L27/115

CPC classification number: H01L21/31053 ,  H01L21/0217 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/324 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7847

Abstract: Improvements are achieved in the properties of a semiconductor device including a MISFET and a nonvolatile memory. Over a gate electrode included in the MISFET and a control gate electrode and a memory gate electrode each included in a memory cell, a stress application film is formed of a silicon nitride film. Then, by removing the silicon nitride film from over the control gate electrode and the memory gate electrode, an opening is formed over the control gate electrode and the memory gate electrode. Then, in a state where the opening is formed in the silicon nitride film, heat treatment is performed to apply a stress to the MISFET. By thus removing the stress application film (silicon nitride film) from over the memory cell, it is possible to avoid the degradation of the properties of the memory cell due to H (hydrogen) in the silicon nitride film.

Abstract translation: 在包括MISFET和非易失性存储器的半导体器件的性能方面实现了改进。 在包括在MISFET中的栅电极和每个包括在存储单元中的控制栅电极和存储栅电极中，应力施加膜由氮化硅膜形成。 然后，通过从控制栅电极和存储栅电极上除去氮化硅膜，在控制栅电极和存储栅极上形成一个开口。 然后，在氮化硅膜中形成开口的状态下，进行热处理，向MISFET施加应力。 通过从存储单元上除去应力施加膜（氮化硅膜），可以避免由于氮化硅膜中的H（氢）导致的存储单元的性质的劣化。

公开(公告)号：US09111636B2

公开(公告)日：2015-08-18

申请号：US14323064

申请日：2014-07-03

Applicant: Renesas Electronics Corporation

Inventor： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC: G11C11/40 ,  G11C11/412 ,  G11C11/413

CPC classification number: G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

公开(公告)号：US09530485B2

公开(公告)日：2016-12-27

申请号：US14826911

申请日：2015-08-14

Applicant: Renesas Electronics Corporation

Inventor： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC: G11C11/40 ,  G11C11/412 ,  G11C11/418 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H03K19/00 ,  G11C11/413

CPC classification number: G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

公开(公告)号：US09324726B2

公开(公告)日：2016-04-26

申请号：US14802050

申请日：2015-07-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Kyoko Umeda ,  Akio Nishida

IPC: H01L21/336 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11573

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.

Abstract translation: 提高了半导体器件的性能。 在制造半导体器件的方法中，在存储单元区域中，在半导体衬底的主表面上形成由第一导电膜形成的控制栅电极。 然后，以覆盖控制栅电极的方式形成绝缘膜和第二导电膜，并且将第二导电膜回蚀刻。 结果，第二导电膜经由绝缘膜留在控制栅电极的侧壁上，从而形成存储栅电极。 然后，在外围电路区域中，在半导体衬底的主表面上形成p型阱。 在p型阱上形成第三导电膜。 然后，形成由第三导电膜形成的栅电极。