公开(公告)号：US08131976B2

公开(公告)日：2012-03-06

申请号：US12422595

申请日：2009-04-13

申请人： Richard W. Doing ,  Susan E. Eisen ,  David S. Levitan ,  Kevin N. Magill ,  Brian R. Mestan ,  Balaram Sinharoy ,  Benjamin W. Stolt ,  Jeffrey R. Summers ,  Albert J. Van Norstrand, Jr.

发明人： Richard W. Doing ,  Susan E. Eisen ,  David S. Levitan ,  Kevin N. Magill ,  Brian R. Mestan ,  Balaram Sinharoy ,  Benjamin W. Stolt ,  Jeffrey R. Summers ,  Albert J. Van Norstrand, Jr.

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/26 ,  G06F9/34

CPC分类号： G06F9/3802 ,  G06F9/322 ,  G06F9/3806 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3861

摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.

摘要翻译： 在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。 这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。 所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。 此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

公开(公告)号：US20100262806A1

公开(公告)日：2010-10-14

申请号：US12422595

申请日：2009-04-13

申请人： Richard W. Doing ,  Susan E. Eisen ,  David S. Levitan ,  Kevin N. Magill ,  Brian R. Mestan ,  Balaram Sinharoy ,  Benjamin W. Stolt ,  Jeffrey R. Summers ,  Albert J. Van Norstrand, JR.

发明人： Richard W. Doing ,  Susan E. Eisen ,  David S. Levitan ,  Kevin N. Magill ,  Brian R. Mestan ,  Balaram Sinharoy ,  Benjamin W. Stolt ,  Jeffrey R. Summers ,  Albert J. Van Norstrand, JR.

IPC分类号： G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/322 ,  G06F9/3806 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3861

摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.

摘要翻译： 在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。 这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。 所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。 此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

公开(公告)号：US20100262813A1

公开(公告)日：2010-10-14

申请号：US12423608

申请日：2009-04-14

申请人： Mary D. Brown ,  Richard W. Doing ,  Kevin N. Magill ,  Brian R. Mestan ,  Wolfram M. Sauer ,  Balaram Sinharoy ,  Jeffrey R. Summers ,  Albert J. Van Norstrand, JR.

发明人： Mary D. Brown ,  Richard W. Doing ,  Kevin N. Magill ,  Brian R. Mestan ,  Wolfram M. Sauer ,  Balaram Sinharoy ,  Jeffrey R. Summers ,  Albert J. Van Norstrand, JR.

IPC分类号： G06F9/38

CPC分类号： G06F9/30003 ,  G06F8/433 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/3855

摘要： Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.

摘要翻译： 在处理器中提供用于检测和处理短前进分支转换候选的机制。 机制识别计算机代码中的条件分支，并确定短向前向条件分支是否要转换为非分支条件指令序列。 此外，机制将条件分支转换为包括解决指令和取决于解析指令的一个或多个条件指令的非分支条件指令序列。 此外，这些机制代替计算机代码中的条件分支执行非分支条件指令序列，并且基于非分支条件指令序列的执行生成计算机代码的输出。

公开(公告)号：US20090063819A1

公开(公告)日：2009-03-05

申请号：US11845838

申请日：2007-08-28

申请人： Richard W. Doing ,  Michael O. Klett ,  Kevin N. Magill ,  Brian R. Mestan ,  David Mui ,  Balaram Sinharoy ,  Jeffrey R. Summers

发明人： Richard W. Doing ,  Michael O. Klett ,  Kevin N. Magill ,  Brian R. Mestan ,  David Mui ,  Balaram Sinharoy ,  Jeffrey R. Summers

IPC分类号： G06F9/312 ,  G06F9/38

CPC分类号： G06F9/3804

摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.

摘要翻译： 用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。 分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。 缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。 替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径 。

公开(公告)号：US07779232B2

公开(公告)日：2010-08-17

申请号：US11845838

申请日：2007-08-28

申请人： Richard W. Doing ,  Michael O. Klett ,  Kevin N. Magill ,  Brian R. Mestan ,  David Mui ,  Balaram Sinharoy ,  Jeffrey R. Summers

发明人： Richard W. Doing ,  Michael O. Klett ,  Kevin N. Magill ,  Brian R. Mestan ,  David Mui ,  Balaram Sinharoy ,  Jeffrey R. Summers

IPC分类号： G06F9/42 ,  G06F9/312

CPC分类号： G06F9/3804

摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.

摘要翻译： 用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。 分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。 缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。 替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径 。

公开(公告)号：US09489207B2

公开(公告)日：2016-11-08

申请号：US12423495

申请日：2009-04-14

申请人： William E. Burky ,  Brian R. Mestan ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

发明人： William E. Burky ,  Brian R. Mestan ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857

摘要： Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group.

摘要翻译： 提供了用于部分刷新处理的机制，每个指令组具有多个分支。 指令提取单元将指令分组分组。 组可以包括浮动分支指令和边界分支指令。 对于每组指令，指令排序单元在全局完成表（GCT）中创建条目，其也可以在此被称为组完成表。 指令排序单元使用GCT来管理每个优秀组内的指令完成。 因为每个组可以包括多达两个分支，所以指令排序单元可以分派指令超出第一分支，即浮动分支。 因此，如果浮动分支导致错误预测，则处理器将对该组进行部分刷新，以及每个小于该组的组的刷新。

公开(公告)号：US20100262967A1

公开(公告)日：2010-10-14

申请号：US12423561

申请日：2009-04-14

申请人： Susan E. Eisen ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

发明人： Susan E. Eisen ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

IPC分类号： G06F9/46

CPC分类号： G06F9/485

摘要： A mechanism is provided for thread completion arbitration. The mechanism comprises executing more than two threads of instructions simultaneously in the processor, selecting a first thread from a first subset of threads, in the more than two threads, for completion of execution within the processor, and selecting a second thread from a second subset of threads, in the more than two threads, for completion of execution within the processor. The mechanism further comprises completing execution of the first and second threads by committing results of the execution of the first and second threads to a storage device associated with the processor. At least one of the first subset of threads or the second subset of threads comprise two or more threads from the more than two threads. The first subset of threads and second subset of threads have different threads from one another.

摘要翻译： 提供线程完成仲裁的机制。 该机制包括在处理器中同时执行多于两个指令的线程，在多于两个线程中从线程的第一子集中选择第一线程，以完成处理器内的执行，以及从第二子集中选择第二线程 的线程，在两个以上的线程中，用于完成处理器内的执行。 该机制还包括通过将执行第一和第二线程的结果提交到与处理器相关联的存储设备来完成第一和第二线程的执行。 线程的第一子集或线程的第二子集中的至少一个包括来自多于两个线程的两个或多个线程。 线程的第一个子集和线程的第二个子集具有彼此不同的线程。

公开(公告)号：US08386753B2

公开(公告)日：2013-02-26

申请号：US12423561

申请日：2009-04-14

申请人： Susan E. Eisen ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

发明人： Susan E. Eisen ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

IPC分类号： G06F9/38

CPC分类号： G06F9/485

摘要： A mechanism is provided for thread completion arbitration. The mechanism comprises executing more than two threads of instructions simultaneously in the processor, selecting a first thread from a first subset of threads, in the more than two threads, for completion of execution within the processor, and selecting a second thread from a second subset of threads, in the more than two threads, for completion of execution within the processor. The mechanism further comprises completing execution of the first and second threads by committing results of the execution of the first and second threads to a storage device associated with the processor. At least one of the first subset of threads or the second subset of threads comprise two or more threads from the more than two threads. The first subset of threads and second subset of threads have different threads from one another.

摘要翻译： 提供线程完成仲裁的机制。 该机制包括在处理器中同时执行多于两个指令的线程，在多于两个线程中从线程的第一子集中选择第一线程，以完成处理器内的执行，以及从第二子集中选择第二线程 的线程，在两个以上的线程中，用于完成处理器内的执行。 该机制还包括通过将执行第一和第二线程的结果提交到与处理器相关联的存储设备来完成第一和第二线程的执行。 线程的第一子集或线程的第二子集中的至少一个包括来自多于两个线程的两个或多个线程。 线程的第一个子集和线程的第二个子集具有彼此不同的线程。

公开(公告)号：US20100262807A1

公开(公告)日：2010-10-14

申请号：US12423495

申请日：2009-04-14

申请人： William E. Burky ,  Brian R. Mestan ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

发明人： William E. Burky ,  Brian R. Mestan ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857

摘要： Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group.

摘要翻译： 提供了用于部分刷新处理的机制，每个指令组具有多个分支。 指令提取单元将指令分组分组。 组可以包括浮动分支指令和边界分支指令。 对于每组指令，指令排序单元在全局完成表（GCT）中创建条目，其也可以在此被称为组完成表。 指令排序单元使用GCT来管理每个优秀组内的指令完成。 因为每个组可以包括多达两个分支，所以指令排序单元可以分派指令超出第一分支，即浮动分支。 因此，如果浮动分支导致错误预测，则处理器将对该组进行部分刷新，以及每个小于该组的组的刷新。

公开(公告)号：US07707396B2

公开(公告)日：2010-04-27

申请号：US11561002

申请日：2006-11-17

申请人： Jeffrey P. Bradford ,  Richard W. Doing ,  Richard J. Eickemeyer ,  Wael R. El-Essawy ,  Douglas R. Logan ,  Balaram Sinharoy ,  William E. Speght ,  Lixin Zhang

发明人： Jeffrey P. Bradford ,  Richard W. Doing ,  Richard J. Eickemeyer ,  Wael R. El-Essawy ,  Douglas R. Logan ,  Balaram Sinharoy ,  William E. Speght ,  Lixin Zhang

IPC分类号： G06F9/00 ,  G06F9/44 ,  G06F7/38

CPC分类号： G06F9/3806 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/3017 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3853

摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.

摘要翻译： 处理器包括一个执行单元和指令排序逻辑，它提取用于执行的指令。 指令排序逻辑包括具有分支目标缓冲器的分支目标地址高速缓存器，该分支目标缓冲器包含多个条目，每个条目将分支指令地址的至少一部分与预测的分支目标地址相关联。 分支目标地址高速缓存使用分支指令地址访问分支目标缓冲器，以获得用作指令获取地址的预测分支目标地址。 分支目标地址缓存还包括缓冲一个或多个候选分支目标地址预测的过滤器缓冲器。 滤波器缓冲器将表示预测精度的各个置信指示与每个候选分支目标地址预测相关联。 分支目标地址缓存基于它们各自的置信度指示来提高从过滤器缓冲器到分支目标缓冲器的候选分支目标地址预测。