公开(公告)号：US11489439B1

公开(公告)日：2022-11-01

申请号：US17468932

申请日：2021-09-08

Applicant: Richtek Technology Corporation

Inventor： Chien-Fu Tang ,  Tzu-Chen Lin ,  Ta-Yung Yang

IPC: H02M1/34 ,  H02M3/335 ,  H02M1/32 ,  H03K3/0233 ,  H02M1/00 ,  G05F1/575 ,  G05F3/18 ,  H02H9/04 ,  G01R19/165

Abstract: A spike suppression circuit includes a wide bandgap transistor, a first transistor, a clamping circuit, and a capacitor. The wide bandgap transistor is depletion-type. The first transistor is coupled in series with the wide bandgap transistor. The clamping circuit provides a voltage difference, and is coupled to a common node between the wide bandgap transistor and the first transistor. The capacitor provides a supply voltage for the clamping circuit. When the first transistor is turned off, the capacitor can recycle spike energy at the common node.

公开(公告)号：US10686383B2

公开(公告)日：2020-06-16

申请号：US16541293

申请日：2019-08-15

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Li-Di Lo ,  Chien-Fu Tang ,  Isaac Y. Chen

IPC: H02M3/335 ,  H03K5/19

Abstract: Whether a synchronous signal includes a synchronous pulse is determined by detecting whether there is a positive pulse higher than a positive threshold followed by a negative pulse lower than a negative threshold. The pulse signal detection method includes: comparing the synchronous signal with the positive threshold; comparing the synchronous signal with the negative threshold; and determining that the synchronous pulse exists when the positive pulse of the synchronous signal is higher than the positive threshold and the negative pulse of the synchronous signal is lower than the negative threshold in a post detection period after the positive pulse of the synchronous signal is determined higher than the positive threshold.

公开(公告)号：US20200036280A1

公开(公告)日：2020-01-30

申请号：US16247520

申请日：2019-01-14

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ta-Yung Yang ,  Tzu-Chen Lin ,  Chien-Fu Tang

IPC: H02M1/08 ,  H02M3/335

Abstract: A ZVS (zero voltage switching) control circuit for use in a flyback power converter includes a primary side controller and a secondary side controller. The primary side controller generates a switching signal to control a power transformer through a power transistor to generate an output voltage. The secondary side controller generates an SR (synchronous rectifier) signal to control an SR transistor at a secondary side of the power transformer. The SR signal includes an SR-control pulse and a ZVS pulse. The SR-control pulse controls the SR transistor according to a demagnetizing period of the power transformer. The ZVS pulse determines the starting timing of the switching signal to achieve zero voltage switching for the power transistor. The secondary side controller generates the ZVS pulse after a delay time from when the power transformer is demagnetized. The delay time is determined according to an output load of the output voltage.

公开(公告)号：US10153703B2

公开(公告)日：2018-12-11

申请号：US15433761

申请日：2017-02-15

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Kuang-Fu Chang ,  Tzu-Chen Lin ,  Chien-Fu Tang

IPC: H02M3/335 ,  H02M1/00

Abstract: The present invention provides a flyback power converter with a programmable output and a control circuit and a control method thereof. The flyback power converter converts an input voltage to a programmable output voltage according to a setting signal, wherein the programmable output voltage switches between different levels. The flyback power converter includes: a transformer circuit, a power switch circuit, a current sense circuit, an opto-coupler circuit, and a control circuit. The control circuit adaptively adjusts an operation signal according to a level of the programmable output voltage, to maintain a same or relatively higher operation frequency of the operation signal when the programmable output voltage switches to a relatively lower level, so as to maintain a phase margin while supplying the same output current.

公开(公告)号：US09966857B2

公开(公告)日：2018-05-08

申请号：US15192187

申请日：2016-06-24

Applicant: Richtek Technology Corporation

Inventor： Jiun-Hung Pan ,  Chien-Fu Tang ,  Jyun-Che Ho ,  Isaac Y. Chen ,  Yu-Chang Chen ,  Jung-Pei Cheng

IPC: H02M3/156 ,  H02M3/335 ,  H02M7/217 ,  H02M1/08 ,  H02M3/157 ,  H02M1/00

CPC classification number: H02M3/33507 ,  H02M1/08 ,  H02M3/156 ,  H02M3/157 ,  H02M3/33515 ,  H02M3/33523 ,  H02M7/217 ,  H02M2001/0009

Abstract: An AC-to-DC power converter with a BJT as a power switch can set a base current of the BJT by a current setting resistor which is in the outside of a control integrated circuit. Since an output current and a recovery current of the BJT are injected into a sensing resistor, the AC-to-DC power converter can correctly detect an inductor current thereof from the sensing resistor.

公开(公告)号：US09964972B2

公开(公告)日：2018-05-08

申请号：US15201476

申请日：2016-07-03

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chien-Fu Tang ,  Jiun-Hung Pan ,  Isaac Y. Chen

IPC: H02M3/157 ,  G05F1/10 ,  H03M1/38 ,  H02M1/00

CPC classification number: G05F1/10 ,  H02M3/157 ,  H02M2001/0025 ,  H03M1/38

Abstract: A mixed mode compensation circuit for a power converter generate a digital signal according to a reference signal and a feedback signal which is related to the output voltage of the power converter, convert the digital signal into a first analog signal, offset the first analog signal with a variable offset value to generate a second analog signal, and filter out high-frequency components of the second analog signal to generate a third analog signal for stable output voltage of the power converter. The mixed mode compensation does not require large capacitors, and thus the circuit can be integrated into an integrated circuit.

公开(公告)号：US09570989B2

公开(公告)日：2017-02-14

申请号：US14669679

申请日：2015-03-26

Applicant: Richtek Technology Corporation

Inventor： Chien-Fu Tang ,  Isaac Y. Chen

IPC: H02J1/02 ,  H02M3/335 ,  H02M1/00

CPC classification number: H02M3/33507 ,  H02M2001/0003 ,  H02M2001/0022 ,  H02M2001/0048 ,  Y02B70/1491

Abstract: A control circuit of a power converter includes: an input signal detection circuit, configured to operably detect a magnitude of an input signal to generate a detection signal; a clock generation circuit, configured to operably generate a clock signal; an error detection circuit, configured to operably generate an error signal according to a reference signal and a feedback signal; a control signal generation circuit, coupled with the clock generation circuit and the error detection circuit, configured to operably control a switching frequency of a power switch according to the clock signal and the error signal; and a reverse adjusting circuit, coupled with the input signal detection circuit, configured to operably adjust the clock generation circuit or the control signal generation circuit according to the detection signal to configure the switching frequency of the power switch to be inversely proportional to the magnitude of the input signal.

Abstract translation: 功率转换器的控制电路包括：输入信号检测电路，被配置为可操作地检测输入信号的幅度以产生检测信号; 时钟生成电路，被配置为可操作地生成时钟信号; 误差检测电路，被配置为根据参考信号和反馈信号可操作地产生误差信号; 与时钟发生电路和误差检测电路耦合的控制信号产生电路被配置为根据时钟信号和误差信号可操作地控制功率开关的开关频率; 以及与所述输入信号检测电路耦合的反向调整电路，被配置为根据所述检测信号可操作地调整所述时钟生成电路或所述控制信号生成电路，以将所述功率开关的开关频率与所述功率开关的开关频率成反比 输入信号。

公开(公告)号：US09450486B2

公开(公告)日：2016-09-20

申请号：US14266566

申请日：2014-04-30

Applicant: Richtek Technology Corporation

Inventor： Chien-Fu Tang ,  Jiun-Hung Pan ,  Isaac Y. Chen

IPC: H02M3/335 ,  H02M3/156 ,  H02M1/00

CPC classification number: H02M3/156 ,  H02M2001/0009

Abstract: An apparatus and a method for implementing a multiple function pin in a boundary conduction mode power supply, uses a same pin to switch a power switch and to achieve zero current detection to reduce pin count and save cost of a control integrated circuit. A first voltage is applied to the multiple function pin to turn on the power switch, and then a second voltage is applied to the multiple function pin after the power switch has been turned on for a first time, to thereby turn off the power switch. After the power switch has been turned off for a second time, a third voltage is applied to the multiple function pin keep the power switch off. Preferably, a tristate output driver is used to provide the first and second voltages, and a clamping circuit is used to provide the third voltage.

Abstract translation: 在边界导通模式电源中实现多功能引脚的装置和方法，使用相同的引脚切换电源开关，实现零电流检测，减少引脚数，节省控制集成电路的成本。 向多功能引脚施加第一电压以接通电源开关，然后在电源开关第一次接通之后，向多功能引脚施加第二电压，从而关闭电源开关。 电源开关第二次关闭后，第三个电压被施加到多功能引脚上，保持电源开关的不动作。 优选地，使用三态输出驱动器来提供第一和第二电压，并且使用钳位电路来提供第三电压。

公开(公告)号：US09104216B2

公开(公告)日：2015-08-11

申请号：US13672125

申请日：2012-11-08

Applicant: Richtek Technology Corporation

Inventor： Chien-Fu Tang ,  Jiun-Hung Pan ,  Isaac Y. Chen

IPC: G05F1/00 ,  G05F1/10

CPC classification number: G05F1/10 ,  H02M1/00 ,  H02M2001/0025 ,  Y02B70/126

Abstract: A mixed mode compensation circuit and method for a power converter generate a digital signal according to a reference value and a feedback signal which is related to the output voltage of the power converter, convert the digital signal into a first analog signal, offset the first analog signal with a variable offset value to generate a second analog signal, and filter out high-frequency components of the second analog signal to generate a third analog signal for stable output voltage of the power converter. The mixed mode compensation does not require large capacitors, and thus the circuit can be integrated into an integrated circuit.

Abstract translation: 用于功率转换器的混合模式补偿电路和方法根据参考值和与功率转换器的输出电压相关的反馈信号产生数字信号，将数字信号转换成第一模拟信号，偏移第一模拟信号 具有可变偏移值的信号以产生第二模拟信号，并且滤除第二模拟信号的高频分量以产生用于功率转换器的稳定输出电压的第三模拟信号。 混合模式补偿不需要大电容器，因此电路可以集成到集成电路中。

公开(公告)号：US11784570B2

公开(公告)日：2023-10-10

申请号：US17367568

申请日：2021-07-05

Applicant: Richtek Technology Corporation

Inventor： Hsin-Yi Wu ,  Chien-Fu Tang

IPC: H02M3/335 ,  H02M7/217 ,  H01L29/78 ,  H03K17/082 ,  G01R19/00

CPC classification number: H02M3/33507 ,  G01R19/0092 ,  H01L29/7803 ,  H01L29/7816 ,  H03K17/0822

Abstract: A power path switch circuit includes: a power transistor unit including: a first vertical double-diffused metal oxide semiconductor (VDMOS) device, wherein a first current outflow end of the first VDMOS device is coupled to an output end of a power path; and a second VDMOS device, wherein a first current inflow end of the first VDMOS device and a second current inflow end of the second VDMOS device are coupled with a supply end of the power path; and a voltage locking circuit coupled to the first current outflow end and the second current outflow end, for locking a voltage at the second current outflow end to a voltage at the first current outflow end, so that there is a predetermined ratio between a first conductive current flowing through the first VDMOS device and a second conductive current flowing through the second VDMOS device.