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17 条记录 (耗时 0.019 秒)

    Constant-current/constant-voltage circuit architecture
    6.
    发明授权
    Constant-current/constant-voltage circuit architecture 有权
    恒流/恒压电路架构

    公开(公告)号：US06700364B2

    公开(公告)日：2004-03-02

    申请号：US10443299

    申请日：2003-05-21

    申请人： Trevor W. Barcelo ,  Robert L. Reay ,  David M. Dwelley

    发明人： Trevor W. Barcelo ,  Robert L. Reay ,  David M. Dwelley

    IPC分类号： G05F316

    CPC分类号： H02M3/158 ,  G05F3/262

    摘要： Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.

    摘要翻译： 提供实现恒流/恒压电路架构的方法和电路。 方法和电路优选地提供一种充电系统，其使用固定电流向负载提供电流，直到负载被充电。 当负载充电时，方法和电路优选地向负载提供可变电流，以便跨过负载保持电压电平。 该可变电流根据负载上的电压而变化。 在本发明的一个实施例中，恒定功率电流也可以用作负载充电电流之一。 恒定功率电流可充当充电电路的功率输出限制。

    Methods and circuitry for interconnecting data and clock busses of live backplane circuitry and input/output card circuitry, and methods and circuitry for isolating capacitanes of a live backplane from the capacitanes of at least one input/output card
    7.
    发明授权
    Methods and circuitry for interconnecting data and clock busses of live backplane circuitry and input/output card circuitry, and methods and circuitry for isolating capacitanes of a live backplane from the capacitanes of at least one input/output card 有权
    用于互连活动背板电路和输入/输出卡电路的数据和时钟总线的方法和电路，以及用于将活动背板的电容器与至少一个输入/输出卡的电容隔离的方法和电路

    公开(公告)号：US07032051B2

    公开(公告)日：2006-04-18

    申请号：US10013893

    申请日：2001-12-11

    申请人： Robert L. Reay ,  John H. Ziegler

    发明人： Robert L. Reay ,  John H. Ziegler

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4081

    摘要： Circuits and methods for interconnecting a live backplane and at least one I/O card are provided. This invention provides interconnection circuitry that utilizes buffer circuitry to connect the data and clock busses of the backplane to the data and clock busses of the I/O card in a “hot-swappable” fashion. Buffer circuitry also isolates the capacitance associated with the backplane from the capacitance associated with the I/O card. For example, when at least one signal is driven from the backplane to the I/O card, the signal need only overcome the capacitance associate with the backplane. Conversely, when at least one signal is driven from the I/O card to the backplane, the signal need only overcome the capacitance associated with the I/O card. Hence, this capacitive isolation facilitates signal propagation between the backplane and the I/O card.

    摘要翻译： 提供了用于互连活动背板和至少一个I / O卡的电路和方法。 本发明提供了互连电路，其利用缓冲电路将背板的数据和时钟总线以“热插拔”方式连接到I / O卡的数据和时钟总线。 缓冲电路还将与背板相关的电容与与I / O卡相关的电容隔离开来。 例如，当至少一个信号从背板驱动到I / O卡时，该信号仅需克服与背板相关联的电容。 相反，当至少一个信号从I / O卡驱动到背板时，信号只需要克服与I / O卡相关的电容。 因此，这种电容隔离有利于背板和I / O卡之间的信号传播。

    Monolithic voltage reference device with internal, multi-temperature drift data and related testing procedures
    8.
    发明授权
    Monolithic voltage reference device with internal, multi-temperature drift data and related testing procedures 有权
    具有内部，多温度漂移数据和相关测试程序的单片电压参考装置

    公开(公告)号：US07920016B2

    公开(公告)日：2011-04-05

    申请号：US12475184

    申请日：2009-05-29

    申请人： Michael B. Anderson ,  Tahir M. Hasoon ,  Brendan J. Whelan ,  J. Spencer Wright ,  Robert L. Reay

    发明人： Michael B. Anderson ,  Tahir M. Hasoon ,  Brendan J. Whelan ,  J. Spencer Wright ,  Robert L. Reay

    IPC分类号： H01L35/00

    CPC分类号： G01R31/2849 ,  G01R31/2874 ,  G01R35/007

    摘要： A testing procedure may determine whether a monolithic voltage reference device meets a temperature drift specification. A first non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a first non-room temperature which is substantially different than room temperature. First non-room temperature information may be stored in a memory within the monolithic voltage reference device which is a function of the first non-room temperature output voltage. A second non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a second non-room temperature which is substantially different than the room temperature and the first non-room temperature. Second non-room temperature information may be stored in the memory without destroying the first non-room temperature information which is a function of the second non-room temperature output voltage. A determination may be made whether the monolithic voltage reference device meets the temperature drift specification based on a computation that is a function of both the first non-room temperature information and the second non-room temperature information.

    摘要翻译： 测试程序可以确定单片电压参考装置是否满足温度漂移规范。 单片电压参考装置的第一非室温输出电压可以被测量，而单片电压参考装置处于与室温基本不同的第一非室温。 第一非室温信息可以存储在作为第一非室温输出电压的函数的单片电压参考装置内的存储器中。 单片电压参考装置的第二非室温输出电压可以被测量，而单片电压参考装置处于与室温和第一非室温基本上不同的第二非室温。 可以将第二非室温信息存储在存储器中，而不破坏作为第二非室温输出电压的函数的第一非室温信息。 可以基于作为第一非室内温度信息和第二非室内温度信息的函数的计算来确定单片电压参考装置是否满足温度漂移规格。

    Schottky enhanced CMOS output circuit
    9.
    再颁专利
    Schottky enhanced CMOS output circuit 失效
    肖特基增强CMOS输出电路

    公开(公告)号：USRE35221E

    公开(公告)日：1996-04-30

    申请号：US61628

    申请日：1993-05-13

    申请人： Robert L. Reay

    发明人： Robert L. Reay

    IPC分类号： H01L27/06 ,  H01L27/092 ,  H03K19/003 ,  H03K19/094 ,  H03K19/0948 ,  H03K19/20

    CPC分类号： H01L27/0629 ,  H01L27/092 ,  H03K19/00315 ,  H03K19/09429 ,  H03K19/0948

    摘要： The high impedance state of a tri-state CMOS transistor output circuit is enhanced by serially connecting first and second Schottky diodes with the P-channel transistor and the N-channel transistor whereby in the high impedance state reverse bias of the substrate/source-drain diodes of the two transistors is prevented when the output of the circuit is taken beyond the supply voltage potentials of the output circuit.

    摘要翻译： 通过将第一和第二肖特基二极管与P沟道晶体管和N沟道晶体管串联连接，增强了三态CMOS晶体管输出电路的高阻抗状态，由此在衬底/源极 - 漏极 当电路的输出超出输出电路的电源电压时，防止两个晶体管的二极管。

    Electrostatic discharge circuit
    10.
    发明授权
    Electrostatic discharge circuit 失效
    静电放电电路

    公开(公告)号：US5485024A

    公开(公告)日：1996-01-16

    申请号：US175991

    申请日：1993-12-30

    申请人： Robert L. Reay

    发明人： Robert L. Reay

    IPC分类号： H01L27/02 ,  H02H9/04 ,  H01L29/74 ,  H01L31/111

    CPC分类号： H01L27/0262 ,  H02H9/046

    摘要： An ESD protection circuit which provides protection for CMOS devices against ESD potentials of up to about 10 kV is provided. The ESD protection circuit is able to provide protection against both positive-going and negative-going high energy electrical transients, and is able to maintain a high impedance state when driven to a voltage beyond the supply rails of CMOS integrated circuit, but less than tile breakdown voltage of the ESD protection circuit. The ESD protection circuit routes currents associated with ESD potentials to a predetermined arbitrary point which may be selected during the fabrication process to meet the needs of a particular application. The structure of the ESD protection circuit permits the holding current to be adjusted to accommodate the current capacity of various external circuits.

    摘要翻译： 提供了ESD保护电路，其为CMOS器件提供高达约10kV的ESD电压的保护。 ESD保护电路能够提供防止正向和负向高能量电瞬变的保护，并且当被驱动到超过CMOS集成电路的电源轨的电压时能够保持高阻抗状态，但是小于瓦 ESD保护电路的击穿电压。 ESD保护电路将与ESD电位相关联的电流路由到在制造过程期间可以选择以满足特定应用的需要的预定任意点。 ESD保护电路的结构允许调整保持电流以适应各种外部电路的电流容量。