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    Method of invoking a low power mode in a computer system using a halt instruction
    6.
    发明授权
    Method of invoking a low power mode in a computer system using a halt instruction 有权
    使用停止指令在计算机系统中调用低功耗模式的方法

    公开(公告)号：US06343363B1

    公开(公告)日：2002-01-29

    申请号：US09570155

    申请日：2000-05-12

    申请人： Robert Maher ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin ,  Mark Bluhm

    发明人： Robert Maher ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin ,  Mark Bluhm

    IPC分类号： G06F132

    CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3867 ,  G06F9/3869 ,  G06F13/4072 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

    摘要： A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) enters the low power operational mode in which power consumption is reduced at least for the pipeline subcircuit, but without stopping the supply of clock signals to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. In a preferred embodiment, the low power operational mode is entered by stopping the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.

    摘要翻译： 在包括耦合到外部逻辑的处理器的计算机系统中使用用于响应于停止指令来调用低功率操作模式的技术。 处理器至少包括（i）用于执行编程指令的管道子电路，包括停止指令，（ii）中断处理子电路以处理由外部中断逻辑产生的中断;以及（iii）向管线提供时钟信号的时钟发生器电路 和中断处理子电路。 响应于停止指令的执行，处理器（i）至少输入管道子电路而进入功率消耗降低的低功率操作模式，但不停止向中断处理子电路提供时钟信号，并且（ii ）向外部逻辑产生一个确认信号，指示管道子电路的时钟信号正在停止，从而进入低功率操作模式。 在优选实施例中，通过停止时钟发生器电路将时钟信号提供给管道子电路而不是中断处理子电路来进入低功率操作模式。 为了恢复正常处理，中断处理子电路通过使时钟发生器电路恢复向管道子电路提供时钟信号，来响应由外部逻辑产生的中断。

    Computer system with low power mode invoked by halt instruction
    7.
    发明授权
    Computer system with low power mode invoked by halt instruction 失效
    通过暂停指令调用低功耗模式的计算机系统

    公开(公告)号：US6088807A

    公开(公告)日：2000-07-11

    申请号：US777772

    申请日：1996-12-09

    申请人： Robert Maher ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin ,  Mark Bluhm

    发明人： Robert Maher ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin ,  Mark Bluhm

    IPC分类号： G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F13/40

    CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/3287 ,  G06F13/4072 ,  G06F9/3869 ,  Y02B60/1221 ,  Y02B60/1235 ,  Y02B60/1282

    摘要： A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) stops the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.

    摘要翻译： 在包括耦合到外部逻辑的处理器的计算机系统中使用用于响应于停止指令来调用低功率操作模式的技术。 处理器至少包括（i）用于执行编程指令的管道子电路，包括停止指令，（ii）中断处理子电路以处理由外部中断逻辑产生的中断;以及（iii）向管线提供时钟信号的时钟发生器电路 和中断处理子电路。 响应于停止指令的执行，处理器（i）停止时钟发生器电路向管道子电路提供时钟信号，而不是中断处理子电路，并且（ii）向外部逻辑产生一个确认信号，指示该 到管道子电路的时钟信号正在停止，从而进入低功率操作模式。 为了恢复正常处理，中断处理子电路通过使时钟发生器电路恢复向管道子电路提供时钟信号，来响应由外部逻辑产生的中断。