利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

35 条记录 (耗时 0.025 秒)

    Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline
    5.
    发明授权
    Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline 失效
    具有多个执行管线的处理器，使用管段状态信息来控制执行管线的管段之间的指令的独立移动

    公开(公告)号：US6138230A

    公开(公告)日：2000-10-24

    申请号：US902908

    申请日：1997-07-29

    申请人： Mark W. Hervin ,  Steven C. McMahan ,  Mark Bluhm ,  Raul A. Garibay, Jr.

    发明人： Mark W. Hervin ,  Steven C. McMahan ,  Mark Bluhm ,  Raul A. Garibay, Jr.

    IPC分类号： G06F9/38 ,  G06F9/00 ,  G06F11/30

    CPC分类号： G06F9/3861 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3875

    摘要： A microprocessor comprises a plurality of instruction pipelines having a plurality of stages for processing a stream of instructions, circuitry for simultaneously issuing instructions into two or more of the pipelines without regard to whether one of the simultaneously issued instructions has a data dependency on other of the simultaneously issued instructions, detecting circuitry for detecting dependencies between instructions in the pipelines and circuitry for controlling the flow of instructions through the pipelines such that an instruction is not delayed due to a data dependency on another instruction unless the data dependency must be resolved for proper processing of the instruction in its current stage.

    摘要翻译： 微处理器包括具有用于处理指令流的多个级的多条指令流水线，用于同时将指令发布到两条或更多条流水线中的电路，而不考虑同时发出的指令之一是否具有与其他 同时发出的指令，用于检测管道中的指令之间的依赖性的检测电路和用于控制通过管线的指令流的电路，使得由于对另一指令的数据依赖性而不指示指令，否则指令不被延迟，除非必须解决数据依赖性以进行适当的处​​理 的指示在当前阶段。

    Distributed search methods, architectures, systems, and software
    7.
    发明申请
    Distributed search methods, architectures, systems, and software 有权
    分布式搜索方法，架构，系统和软件

    公开(公告)号：US20050004898A1

    公开(公告)日：2005-01-06

    申请号：US10832094

    申请日：2004-04-26

    申请人： Mark Bluhm

    发明人： Mark Bluhm

    IPC分类号： G06F17/30 ,  G06F7/00

    CPC分类号： G06F17/30864

    摘要： Systems, methods, and software for providing a distributed search function for online delivery platforms used in law firms and other enterprises are described. For example, one aspect of the systems, methods and software provides a plurality of data sets. The data sets may comprise indices into other sets of data. At least one search engine is associated with each data set. A system receiving a search request determines which search engines are used to process the search request based on the data sets involved in the search request. The search request is then forwarded to the identified search engines.

    摘要翻译： 描述了为律师事务所和其他企业使用的在线交付平台提供分布式搜索功能的系统，方法和软件。 例如，系统，方法和软件的一个方面提供多个数据集。 数据集可以包括指向其他​​数据集的索引。 至少一个搜索引擎与每个数据集相关联。 接收搜索请求的系统基于搜索请求中涉及的数据集确定使用哪些搜索引擎来处理搜索请求。 然后将搜索请求转发到所识别的搜索引擎。

    Method of invoking a low power mode in a computer system using a halt instruction
    9.
    发明授权
    Method of invoking a low power mode in a computer system using a halt instruction 有权
    使用停止指令在计算机系统中调用低功耗模式的方法

    公开(公告)号：US06343363B1

    公开(公告)日：2002-01-29

    申请号：US09570155

    申请日：2000-05-12

    申请人： Robert Maher ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin ,  Mark Bluhm

    发明人： Robert Maher ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin ,  Mark Bluhm

    IPC分类号： G06F132

    CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3867 ,  G06F9/3869 ,  G06F13/4072 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

    摘要： A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) enters the low power operational mode in which power consumption is reduced at least for the pipeline subcircuit, but without stopping the supply of clock signals to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. In a preferred embodiment, the low power operational mode is entered by stopping the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.

    摘要翻译： 在包括耦合到外部逻辑的处理器的计算机系统中使用用于响应于停止指令来调用低功率操作模式的技术。 处理器至少包括（i）用于执行编程指令的管道子电路，包括停止指令，（ii）中断处理子电路以处理由外部中断逻辑产生的中断;以及（iii）向管线提供时钟信号的时钟发生器电路 和中断处理子电路。 响应于停止指令的执行，处理器（i）至少输入管道子电路而进入功率消耗降低的低功率操作模式，但不停止向中断处理子电路提供时钟信号，并且（ii ）向外部逻辑产生一个确认信号，指示管道子电路的时钟信号正在停止，从而进入低功率操作模式。 在优选实施例中，通过停止时钟发生器电路将时钟信号提供给管道子电路而不是中断处理子电路来进入低功率操作模式。 为了恢复正常处理，中断处理子电路通过使时钟发生器电路恢复向管道子电路提供时钟信号，来响应由外部逻辑产生的中断。

    Computer system with low power mode invoked by halt instruction
    10.
    发明授权
    Computer system with low power mode invoked by halt instruction 失效
    通过暂停指令调用低功耗模式的计算机系统

    公开(公告)号：US6088807A

    公开(公告)日：2000-07-11

    申请号：US777772

    申请日：1996-12-09

    申请人： Robert Maher ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin ,  Mark Bluhm

    发明人： Robert Maher ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin ,  Mark Bluhm

    IPC分类号： G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F13/40

    CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/3287 ,  G06F13/4072 ,  G06F9/3869 ,  Y02B60/1221 ,  Y02B60/1235 ,  Y02B60/1282

    摘要： A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) stops the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.

    摘要翻译： 在包括耦合到外部逻辑的处理器的计算机系统中使用用于响应于停止指令来调用低功率操作模式的技术。 处理器至少包括（i）用于执行编程指令的管道子电路，包括停止指令，（ii）中断处理子电路以处理由外部中断逻辑产生的中断;以及（iii）向管线提供时钟信号的时钟发生器电路 和中断处理子电路。 响应于停止指令的执行，处理器（i）停止时钟发生器电路向管道子电路提供时钟信号，而不是中断处理子电路，并且（ii）向外部逻辑产生一个确认信号，指示该 到管道子电路的时钟信号正在停止，从而进入低功率操作模式。 为了恢复正常处理，中断处理子电路通过使时钟发生器电路恢复向管道子电路提供时钟信号，来响应由外部逻辑产生的中断。