公开(公告)号：US5874931A

公开(公告)日：1999-02-23

申请号：US671962

申请日：1996-06-28

Applicant: Rodney Drake ,  Ray Allen

Inventor： Rodney Drake ,  Ray Allen

IPC: G02F1/133 ,  G06F3/147 ,  G09G3/18 ,  G09G3/20 ,  G09G3/36

CPC classification number: G06F3/147 ,  G09G3/18 ,  G09G3/3696

Abstract: A single semiconductor chip device is utilized for controlling an external system which has a liquid crystal display (LCD) associated therewith. A dual port random access memory (RAM) stores data representative of information to be displayed on the LCD. The RAM includes a plurality of master data storage latches and a single slave data storage latch shared by all of the plurality of master storage latches. A microcontroller has a central processing unit (CPU) for communicating with the master storage latches via one of the RAM ports to periodically change the data stored therein. An LCD control module successively updates the data in the single slave storage latch with data from each of the master storage latches and downloads the updated data from the single slave storage latch to a temporary store associated with the LCD after each update from a master storage latch and before the update of data from the next master storage latch. Consequently, data in each master storage latch may be changed periodically by the CPU without interference with downloading of updated data from the single slave storage unit.

Abstract translation: 单个半导体芯片装置用于控制具有与其相关联的液晶显示器（LCD）的外部系统。 双端口随机存取存储器（RAM）存储表示要显示在LCD上的信息的数据。 RAM包括多个主数据存储锁存器和由所有多个主存储锁存器共享的单个从属数据存储锁存器。 微控制器具有中央处理单元（CPU），用于经由一个RAM端口与主存储锁存器进行通信，以周期性地改变存储在其中的数据。 LCD控制模块使用来自每个主存储锁存器的数据连续地更新单个从存储锁存器中的数据，并且在从主存储器锁存器每次更新之后将更新的数据从单个从存储锁存器下载到与LCD相关联的临时存储器 并在更新下一个主存储锁存器的数据之前。 因此，每个主存储锁存器中的数据可以由CPU周期性地改变，而不会干扰来自单个从存储单元的更新数据的下载。

公开(公告)号：US5473758A

公开(公告)日：1995-12-05

申请号：US938911

申请日：1992-08-31

Applicant: Ray Allen ,  Sumit Mitra ,  Rodney Drake

Inventor： Ray Allen ,  Sumit Mitra ,  Rodney Drake

IPC: G11C16/10 ,  G06F15/02

CPC classification number: G11C16/102

Abstract: A microcontroller and associated EPROM program memory are fabricated in a single semiconductor chip. The microcontroller device is adapted to be programmed using digital command words or other bit patterns applied as inputs after installation of the device in circuit with a system to be controlled by the device, and to have its programming pins isolated from the system to avoid effects on system operation while the programming is taking place. The in-circuit programming uses considerably less than the total number of input/output (I/O) pins of the device, which in total are fewer than the number of bits in a command word. This is achieved with a serial/parallel programming interface between the pins and the program memory, and by applying the data in serial fashion to the interface where it is latched and loaded in parallel in the memory. Input data to the device may alternatively be entered in parallel to the interface in bytes of width less than the total number of I/O pins of the device.

Abstract translation: 在单个半导体芯片中制造微控制器和相关联的EPROM程序存储器。 微控制器设备适于在使用要由设备控制的系统安装设备的电路中的数字命令字或其他位模式中使用数字命令字或其他位模式进行编程，并将其编程引脚与系统隔离以避免对 系统运行时正在进行编程。 在线编程使用量远低于设备的输入/输出（I / O）引脚总数，总共少于命令字中的位数。 这是通过引脚和程序存储器之间的串行/并行编程接口实现的，并且通过将数据以串行方式应用于其被锁存并且并行加载到存储器中的接口来实现。 输入到设备的数据可以替代地以与字节相同的字节并行输入，该字节的宽度小于设备的I / O引脚的总数。

公开(公告)号：US5351216A

公开(公告)日：1994-09-27

申请号：US26908

申请日：1993-03-05

Applicant: Tom Salt ,  Rodney Drake ,  Ray Allen

Inventor： Tom Salt ,  Rodney Drake ,  Ray Allen

IPC: G05B19/042 ,  G06F11/14 ,  G11C16/22 ,  G06K5/00

CPC classification number: G05B19/0428 ,  G06F11/1402 ,  G11C16/22 ,  G05B2219/23215 ,  G05B2219/23345 ,  G05B2219/25301

Abstract: A single chip, semiconductor microcontroller device is adapted to control an aspect of the operation of an external system. The device includes a CPU, program memory for storing instructions to be selectively executed by the CPU to perform the control functions, and peripheral EEPROM data memory adapted to be written to for storing selected data in selected ones of a multiplicity of addresses of the data memory and for selective retrieval of the stored dam by the CPU within its control function. Internal logic in the device is implemented to abort a write operation in progress on the EEPROM data memory upon occurrence of an asynchronous reset of the device. An error flag is set by the logic to indicate that the write operation is being aborted, and the data that was partially written to the EEPROM memory at the time the write operation was aborted is held intact.

Abstract translation: 单芯片半导体微控制器装置适于控制外部系统的操作的一个方面。 该装置包括CPU，用于存储由CPU选择性地执行以执行控制功能的指令的程序存储器，以及适于被写入以便将选择的数据存储在数据存储器的多个地址中的选定数据中的外围EEPROM数据存储器 并且用于在其控制功能内由CPU选择性地检索存储的水坝。 器件的内部逻辑被实现为在器件的异步复位发生时中止EEPROM数据存储器上正在进行的写入操作。 由逻辑设置错误标志以指示写入操作正在中止，并且在写入操作中止时部分写入EEPROM存储器的数据保持不变。

公开(公告)号：US5455937A

公开(公告)日：1995-10-03

申请号：US268673

申请日：1994-06-30

Applicant: Eric Berman ,  Greg Italiano ,  Ajay Padgaonkar ,  Ray Allen

Inventor： Eric Berman ,  Greg Italiano ,  Ajay Padgaonkar ,  Ray Allen

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/26 ,  G06F11/267 ,  G06F15/78 ,  G11C7/00 ,  G01R31/28

CPC classification number: G06F9/30145 ,  G06F11/2236 ,  G06F11/261 ,  G06F15/7814 ,  G06F9/30167

Abstract: A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory with programmable EPROM configuration fuses located in a limited number of addresses of the on-chip program memory, the condition of each of EPROM fuse being defined as blown or not blown according to the value of the bit stored in the respective address of the on-chip program memory. The operating modes of the microcontroller are configurable by appropriately programming at least some of the EPROM fuses. Testing of the microcontroller in at least some of the operating modes is achieved by using latches outside the program memory to emulate the EPROM fuses, while suppressing the capability to set the condition of the EPROM fuses during the testing. Upon completion of the testing, control of the operating modes of the microcontroller is returned to the EPROM fuses, and the latches are precluded from further emulating the EPROM fuses.

Abstract translation: 在半导体芯片上制造的微控制器具有片上EPROM程序存储器，其具有位于片上程序存储器的有限地址中的可编程EPROM配置熔丝，每个EPROM保险丝的条件被定义为被吹制或不被吹制 到存储在片上程序存储器的相应地址中的位的值。 微控制器的工作模式可以通过适当地编程至少一些EPROM保险丝进行配置。 在至少一些操作模式下对微控制器的测试通过使用程序存储器外部的锁存器来模拟EPROM保险丝，同时抑制在测试期间设置EPROM保险丝的状态的能力来实现。 完成测试后，控制微控制器的工作模式返回到EPROM保险丝，锁存器不再进一步仿真EPROM保险丝。

公开(公告)号：US5446864A

公开(公告)日：1995-08-29

申请号：US207886

申请日：1994-03-07

Applicant: Martin Burghardt ,  Eric Berman ,  Ajay Padgaonkar ,  Ray Allen

Inventor： Martin Burghardt ,  Eric Berman ,  Ajay Padgaonkar ,  Ray Allen

IPC: G06F12/14

CPC classification number: G06F12/1433

Abstract: A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory. The microcontroller is selectively configurable to operate in any one of a plurality of predetermined operating modes, including at least one secure microcontroller mode. A plurality of EPROM configuration fuses used for configuring the microcontroller and protecting its program memory from read, verify or write through any instruction initiated from other than a predetermined secure area of the chip, are mapped into the on-chip EPROM program memory as bits in respective address locations thereof. The value of a bit representing any one of said fuses is effective to determine the condition of the respective fuse. That condition is observed by reading the value of the respective bit for that fuse stored in the EPROM program memory. The chip security is enabled by configuring the microcontroller in a code protected mode by programming the bits representing the desired fuses in the EPROM program memory to effectively blow or erase each fuse according to the desired configuration.

Abstract translation: 在半导体芯片上制造的微控制器具有片上EPROM程序存储器。 微控制器被选择性地配置为以多个预定操作模式中的任一种操作，包括至少一个安全微控制器模式。 用于配置微控制器并保护其程序存储器的多个EPROM配置保险丝不被从芯片的预定安全区域以外发起的任何指令的读取，验证或写入，被映射到片上EPROM程序存储器中，作为 各自的地址位置。 表示任何一个所述保险丝的位的值对于确定相应保险丝的状态是有效的。 通过读取存储在EPROM程序存储器中的该熔丝的相应位的值来观察该条件。 通过将代表EPROM程序存储器中所需保险丝的位编程为根据所需配置有效地吹扫或擦除每个保险丝，可以通过将代码保护模式中的微控制器配置为芯片安全性。

公开(公告)号：US5737548A

公开(公告)日：1998-04-07

申请号：US554741

申请日：1995-11-07

Applicant: Randy L. Yach ,  Ray Allen

Inventor： Randy L. Yach ,  Ray Allen

IPC: G06F15/78 ,  G06F13/00

CPC classification number: G06F15/7814

Abstract: A RISC-based microcontroller is described which uses "split" data buses in the functional areas of the ALU and the I/O peripheral control interface. Also, the "Harvard" architecture is applied with separate buses for instructions and operational data which are stored and supplied from separate memories, i.e., an instruction memory and a data memory. This architecture allows to run the microcontroller with timing and clocking schemes of higher frequencies resulting in faster speed and higher processing rates in MIPS. The different functional components of the microcontroller can be placed on a single VLSI chip while other designs with much less on-chip functions are also conceivable.

Abstract translation: 描述了基于RISC的微控制器，其在ALU和I / O外围设备控制接口的功能区域中使用“分割”数据总线。 此外，“哈佛”架构被应用于单独的总线，用于从单独的存储器即指令存储器和数据存储器存储和提供的指令和操作数据。 该架构允许以更高频率的定时和时钟方案运行微控制器，从而在MIPS中实现更快的速度和更高的处理速率。 微控制器的不同功能组件可以放置在单个VLSI芯片上，而其他具有更少片上功能的设计也是可以想到的。